From patchwork Mon Jul 3 13:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1802754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Qvn2V0bwHz20bT for ; Mon, 3 Jul 2023 23:34:10 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGJaN-00045r-MN; Mon, 03 Jul 2023 09:27:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGJZw-0003t5-Ml for qemu-devel@nongnu.org; Mon, 03 Jul 2023 09:26:57 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGJZu-00014D-FH for qemu-devel@nongnu.org; Mon, 03 Jul 2023 09:26:56 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4Qvmt42KGnz4wxr; Mon, 3 Jul 2023 23:26:52 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4Qvmt215WHz4wqZ; Mon, 3 Jul 2023 23:26:49 +1000 (AEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bin Meng , Peter Maydell , Lucien Murray-Pitts , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Subject: [PATCH 32/32] aspeed: Introduce a 'boot-emmc' property for AST2600 based machines Date: Mon, 3 Jul 2023 15:25:09 +0200 Message-ID: <20230703132509.2474225-33-clg@kaod.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230703132509.2474225-1-clg@kaod.org> References: <20230703132509.2474225-1-clg@kaod.org> MIME-Version: 1.0 Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=mKPa=CV=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 2 ++ hw/arm/aspeed.c | 42 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 80538422a1a4..157bfcc8f396 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -113,6 +113,8 @@ The image should be attached as an MTD drive. Run : Options specific to Aspeed machines are : + * ``boot-emmc`` to set or unset boot from eMMC (AST2600 only). + * ``execute-in-place`` which emulates the boot from the CE0 flash device by using the FMC controller to load the instructions, and not simply from RAM. This takes a little longer. diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6631552358d1..dde8dc62a87e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -46,6 +46,7 @@ struct AspeedMachineState { uint32_t uart_chosen; char *fmc_model; char *spi_model; + uint32_t hw_strap1; }; /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ @@ -370,7 +371,7 @@ static void aspeed_machine_init(MachineState *machine) sc = ASPEED_SOC_GET_CLASS(&bmc->soc); boot_emmc = sc->boot_emmc && - !!(amc->hw_strap1 & AST26500_HW_STRAP_BOOT_SRC_EMMC); + !!(bmc->hw_strap1 & AST26500_HW_STRAP_BOOT_SRC_EMMC); /* * This will error out if the RAM size is not supported by the @@ -387,7 +388,7 @@ static void aspeed_machine_init(MachineState *machine) } } - object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, + object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", bmc->hw_strap1, &error_abort); object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, &error_abort); @@ -1069,7 +1070,10 @@ static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) static void aspeed_machine_instance_init(Object *obj) { + AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); + ASPEED_MACHINE(obj)->mmio_exec = false; + ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; } static char *aspeed_get_fmc_model(Object *obj, Error **errp) @@ -1349,6 +1353,32 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; +static bool aspeed_get_boot_emmc(Object *obj, Error **errp) +{ + AspeedMachineState *bmc = ASPEED_MACHINE(obj); + + return !!(bmc->hw_strap1 & AST26500_HW_STRAP_BOOT_SRC_EMMC); +} + +static void aspeed_set_boot_emmc(Object *obj, bool value, Error **errp) +{ + AspeedMachineState *bmc = ASPEED_MACHINE(obj); + + if (value) { + bmc->hw_strap1 |= AST26500_HW_STRAP_BOOT_SRC_EMMC; + } else { + bmc->hw_strap1 &= ~AST26500_HW_STRAP_BOOT_SRC_EMMC; + } +} + +static void aspeed_machine_ast2600_class_init(ObjectClass *oc, void *data) +{ + object_class_property_add_bool(oc, "boot-emmc", aspeed_get_boot_emmc, + aspeed_set_boot_emmc); + object_class_property_set_description(oc, "boot-emmc", + "Set or unset boot from EMMC"); +} + static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1367,6 +1397,8 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); + + aspeed_machine_ast2600_class_init(oc, data); }; static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) @@ -1386,6 +1418,8 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); + + aspeed_machine_ast2600_class_init(oc, data); }; static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) @@ -1441,6 +1475,8 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); + + aspeed_machine_ast2600_class_init(oc, data); }; #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) @@ -1463,6 +1499,8 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) mc->default_ram_size = FUJI_BMC_RAM_SIZE; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); + + aspeed_machine_ast2600_class_init(oc, data); }; #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)