[v2,27/46] target/loongarch: Implement xvsrlr xvsrar

Message ID	20230630075904.45940-28-gaosong@loongson.cn
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Song Gao <gaosong@loongson.cn> To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH v2 27/46] target/loongarch: Implement xvsrlr xvsrar Date: Fri, 30 Jun 2023 15:58:45 +0800 Message-Id: <20230630075904.45940-28-gaosong@loongson.cn> In-Reply-To: <20230630075904.45940-1-gaosong@loongson.cn> References: <20230630075904.45940-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	Add LoongArch LASX instructions \| expand [v2,00/46] Add LoongArch LASX instructions [v2,01/46] target/loongarch: Add LASX data support [v2,02/46] target/loongarch: meson.build support build LASX [v2,03/46] target/loongarch: Add CHECK_ASXE maccro for check LASX enable [v2,04/46] target/loongarch: Implement xvadd/xvsub [v2,05/46] target/loongarch: Implement xvreplgr2vr [v2,06/46] target/loongarch: Implement xvaddi/xvsubi [v2,07/46] target/loongarch: Implement xvneg [v2,08/46] target/loongarch: Implement xvsadd/xvssub [v2,09/46] target/loongarch: Implement xvhaddw/xvhsubw [v2,10/46] target/loongarch: Implement xvaddw/xvsubw [v2,11/46] target/loongarch: Implement xavg/xvagr [v2,12/46] target/loongarch: Implement xvabsd [v2,13/46] target/loongarch: Implement xvadda [v2,14/46] target/loongarch: Implement xvmax/xvmin [v2,15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od} [v2,16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od} [v2,17/46] target/loongarch; Implement xvdiv/xvmod [v2,18/46] target/loongarch: Implement xvsat [v2,19/46] target/loongarch: Implement xvexth [v2,20/46] target/loongarch: Implement vext2xv [v2,21/46] target/loongarch: Implement xvsigncov [v2,22/46] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz [v2,23/46] target/loognarch: Implement xvldi [v2,24/46] target/loongarch: Implement LASX logic instructions [v2,25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr [v2,26/46] target/loongarch: Implement xvsllwil xvextl [v2,27/46] target/loongarch: Implement xvsrlr xvsrar [v2,28/46] target/loongarch: Implement xvsrln xvsran [v2,29/46] target/loongarch: Implement xvsrlrn xvsrarn [v2,30/46] target/loongarch: Implement xvssrln xvssran [v2,31/46] target/loongarch: Implement xvssrlrn xvssrarn [v2,32/46] target/loongarch: Implement xvclo xvclz [v2,33/46] target/loongarch: Implement xvpcnt [v2,34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev [v2,35/46] target/loongarch: Implement xvfrstp [v2,36/46] target/loongarch: Implement LASX fpu arith instructions [v2,37/46] target/loongarch: Implement LASX fpu fcvt instructions [v2,38/46] target/loongarch: Implement xvseq xvsle xvslt [v2,39/46] target/loongarch: Implement xvfcmp [v2,40/46] target/loongarch: Implement xvbitsel xvset [v2,41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr [v2,42/46] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v [v2,43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h} [v2,44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins [v2,45/46] target/loongarch: Implement xvld xvst [v2,46/46] target/loongarch: CPUCFG support LASX

diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 93c205fa32..9109203a05 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -2086,6 +2086,24 @@ INSN_LASX(xvsllwil_wu_hu, vv_i) INSN_LASX(xvsllwil_du_wu, vv_i) INSN_LASX(xvextl_qu_du, vv) +INSN_LASX(xvsrlr_b, vvv) +INSN_LASX(xvsrlr_h, vvv) +INSN_LASX(xvsrlr_w, vvv) +INSN_LASX(xvsrlr_d, vvv) +INSN_LASX(xvsrlri_b, vv_i) +INSN_LASX(xvsrlri_h, vv_i) +INSN_LASX(xvsrlri_w, vv_i) +INSN_LASX(xvsrlri_d, vv_i) + +INSN_LASX(xvsrar_b, vvv) +INSN_LASX(xvsrar_h, vvv) +INSN_LASX(xvsrar_w, vvv) +INSN_LASX(xvsrar_d, vvv) +INSN_LASX(xvsrari_b, vv_i) +INSN_LASX(xvsrari_h, vv_i) +INSN_LASX(xvsrari_w, vv_i) +INSN_LASX(xvsrari_d, vv_i) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 81c3ad4cc0..b4828b1829 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -375,23 +375,23 @@ DEF_HELPER_5(vsllwil_wu_hu, void, env, i32, i32, i32, i32) DEF_HELPER_5(vsllwil_du_wu, void, env, i32, i32, i32, i32) DEF_HELPER_4(vextl_qu_du, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlr_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlr_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlr_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlr_d, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrlri_d, void, env, i32, i32, i32) - -DEF_HELPER_4(vsrar_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsrar_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrar_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrar_d, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_b, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_h, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_w, void, env, i32, i32, i32) -DEF_HELPER_4(vsrari_d, void, env, i32, i32, i32) +DEF_HELPER_5(vsrlr_b, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlr_h, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlr_w, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlr_d, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlri_b, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlri_h, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlri_w, void, env, i32, i32, i32, i32) +DEF_HELPER_5(vsrlri_d, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(vsrar_b, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrar_h, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrar_w, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrar_d, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrari_b, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrari_h, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrari_w, void, env, int, i32, i32, i32) +DEF_HELPER_5(vsrari_d, void, env, int, i32, i32, i32) DEF_HELPER_4(vsrln_b_h, void, env, i32, i32, i32) DEF_HELPER_4(vsrln_h_w, void, env, i32, i32, i32) diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc b/target/loongarch/insn_trans/trans_lasx.c.inc index 497940b6fd..2f654ef401 100644 --- a/target/loongarch/insn_trans/trans_lasx.c.inc +++ b/target/loongarch/insn_trans/trans_lasx.c.inc @@ -462,6 +462,24 @@ TRANS(xvsllwil_wu_hu, gen_vv_i, 32, gen_helper_vsllwil_wu_hu) TRANS(xvsllwil_du_wu, gen_vv_i, 32, gen_helper_vsllwil_du_wu) TRANS(xvextl_qu_du, gen_vv, 32, gen_helper_vextl_qu_du) +TRANS(xvsrlr_b, gen_vvv, 32, gen_helper_vsrlr_b) +TRANS(xvsrlr_h, gen_vvv, 32, gen_helper_vsrlr_h) +TRANS(xvsrlr_w, gen_vvv, 32, gen_helper_vsrlr_w) +TRANS(xvsrlr_d, gen_vvv, 32, gen_helper_vsrlr_d) +TRANS(xvsrlri_b, gen_vv_i, 32, gen_helper_vsrlri_b) +TRANS(xvsrlri_h, gen_vv_i, 32, gen_helper_vsrlri_h) +TRANS(xvsrlri_w, gen_vv_i, 32, gen_helper_vsrlri_w) +TRANS(xvsrlri_d, gen_vv_i, 32, gen_helper_vsrlri_d) + +TRANS(xvsrar_b, gen_vvv, 32, gen_helper_vsrar_b) +TRANS(xvsrar_h, gen_vvv, 32, gen_helper_vsrar_h) +TRANS(xvsrar_w, gen_vvv, 32, gen_helper_vsrar_w) +TRANS(xvsrar_d, gen_vvv, 32, gen_helper_vsrar_d) +TRANS(xvsrari_b, gen_vv_i, 32, gen_helper_vsrari_b) +TRANS(xvsrari_h, gen_vv_i, 32, gen_helper_vsrari_h) +TRANS(xvsrari_w, gen_vv_i, 32, gen_helper_vsrari_w) +TRANS(xvsrari_d, gen_vv_i, 32, gen_helper_vsrari_d) + TRANS(xvreplgr2vr_b, gvec_dup, 32, MO_8) TRANS(xvreplgr2vr_h, gvec_dup, 32, MO_16) TRANS(xvreplgr2vr_w, gvec_dup, 32, MO_32) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 8a7933eccc..ca0951e1cc 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1661,6 +1661,23 @@ xvsllwil_wu_hu 0111 01110000 11000 1 .... ..... ..... @vv_ui4 xvsllwil_du_wu 0111 01110000 11001 ..... ..... ..... @vv_ui5 xvextl_qu_du 0111 01110000 11010 00000 ..... ..... @vv +xvsrlr_b 0111 01001111 00000 ..... ..... ..... @vvv +xvsrlr_h 0111 01001111 00001 ..... ..... ..... @vvv +xvsrlr_w 0111 01001111 00010 ..... ..... ..... @vvv +xvsrlr_d 0111 01001111 00011 ..... ..... ..... @vvv +xvsrlri_b 0111 01101010 01000 01 ... ..... ..... @vv_ui3 +xvsrlri_h 0111 01101010 01000 1 .... ..... ..... @vv_ui4 +xvsrlri_w 0111 01101010 01001 ..... ..... ..... @vv_ui5 +xvsrlri_d 0111 01101010 0101 ...... ..... ..... @vv_ui6 +xvsrar_b 0111 01001111 00100 ..... ..... ..... @vvv +xvsrar_h 0111 01001111 00101 ..... ..... ..... @vvv +xvsrar_w 0111 01001111 00110 ..... ..... ..... @vvv +xvsrar_d 0111 01001111 00111 ..... ..... ..... @vvv +xvsrari_b 0111 01101010 10000 01 ... ..... ..... @vv_ui3 +xvsrari_h 0111 01101010 10000 1 .... ..... ..... @vv_ui4 +xvsrari_w 0111 01101010 10001 ..... ..... ..... @vv_ui5 +xvsrari_d 0111 01101010 1001 ...... ..... ..... @vv_ui6 + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index 58b2b7da12..b745240f8c 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -1012,15 +1012,16 @@ do_vsrlr(W, uint32_t) do_vsrlr(D, uint64_t) #define VSRLR(NAME, BIT, T, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ +void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \ uint32_t vd, uint32_t vj, uint32_t vk) \ { \ - int i; \ + int i, len; \ VReg *Vd = &(env->fpr[vd].vreg); \ VReg *Vj = &(env->fpr[vj].vreg); \ VReg *Vk = &(env->fpr[vk].vreg); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ + len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \ + for (i = 0; i < len / BIT; i++) { \ Vd->E(i) = do_vsrlr_ ## E(Vj->E(i), ((T)Vk->E(i))%BIT); \ } \ } @@ -1031,14 +1032,15 @@ VSRLR(vsrlr_w, 32, uint32_t, W) VSRLR(vsrlr_d, 64, uint64_t, D) #define VSRLRI(NAME, BIT, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ +void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \ uint32_t vd, uint32_t vj, uint32_t imm) \ { \ - int i; \ + int i, len; \ VReg *Vd = &(env->fpr[vd].vreg); \ VReg *Vj = &(env->fpr[vj].vreg); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ + len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \ + for (i = 0; i < len / BIT; i++) { \ Vd->E(i) = do_vsrlr_ ## E(Vj->E(i), imm); \ } \ } @@ -1064,15 +1066,16 @@ do_vsrar(W, int32_t) do_vsrar(D, int64_t) #define VSRAR(NAME, BIT, T, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ +void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \ uint32_t vd, uint32_t vj, uint32_t vk) \ { \ - int i; \ + int i, len; \ VReg *Vd = &(env->fpr[vd].vreg); \ VReg *Vj = &(env->fpr[vj].vreg); \ VReg *Vk = &(env->fpr[vk].vreg); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ + len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \ + for (i = 0; i < len / BIT; i++) { \ Vd->E(i) = do_vsrar_ ## E(Vj->E(i), ((T)Vk->E(i))%BIT); \ } \ } @@ -1083,14 +1086,15 @@ VSRAR(vsrar_w, 32, uint32_t, W) VSRAR(vsrar_d, 64, uint64_t, D) #define VSRARI(NAME, BIT, E) \ -void HELPER(NAME)(CPULoongArchState *env, \ +void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \ uint32_t vd, uint32_t vj, uint32_t imm) \ { \ - int i; \ + int i, len; \ VReg *Vd = &(env->fpr[vd].vreg); \ VReg *Vj = &(env->fpr[vj].vreg); \ \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ + len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \ + for (i = 0; i < len / BIT; i++) { \ Vd->E(i) = do_vsrar_ ## E(Vj->E(i), imm); \ } \ }

[v2,27/46] target/loongarch: Implement xvsrlr xvsrar

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Patch