diff mbox series

mv64361: Add dummy gigabit ethernet PHY access registers

Message ID 20230605215145.29458746335@zero.eik.bme.hu
State New
Headers show
Series mv64361: Add dummy gigabit ethernet PHY access registers | expand

Commit Message

BALATON Zoltan June 5, 2023, 9:51 p.m. UTC
We don't emulate the gigabit ethernet part of the chip but the MorphOS
driver accesses these and expects to get some valid looking result
otherwise it hangs. Add some minimal dummy implementation to avoid rhis.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
This is only used by MorphOS on pegasos2 so most likely could go via
the ppc queue.

 hw/pci-host/mv64361.c | 6 ++++++
 hw/pci-host/mv643xx.h | 3 +++
 2 files changed, 9 insertions(+)

Comments

BALATON Zoltan June 14, 2023, 7:21 p.m. UTC | #1
On Mon, 5 Jun 2023, BALATON Zoltan wrote:
> We don't emulate the gigabit ethernet part of the chip but the MorphOS
> driver accesses these and expects to get some valid looking result
> otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> This is only used by MorphOS on pegasos2 so most likely could go via
> the ppc queue.

Ping?

Regards,
BALATON Zoltan

> hw/pci-host/mv64361.c | 6 ++++++
> hw/pci-host/mv643xx.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
> index 19e8031a3f..01bd8c887f 100644
> --- a/hw/pci-host/mv64361.c
> +++ b/hw/pci-host/mv64361.c
> @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
>             }
>         }
>         break;
> +    case MV64340_ETH_PHY_ADDR:
> +        ret = 0x98;
> +        break;
> +    case MV64340_ETH_SMI:
> +        ret = BIT(27);
> +        break;
>     case MV64340_CUNIT_ARBITER_CONTROL_REG:
>         ret = 0x11ff0000 | (s->gpp_int_level << 10);
>         break;
> diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
> index cd26a43f18..f2e1baea88 100644
> --- a/hw/pci-host/mv643xx.h
> +++ b/hw/pci-host/mv643xx.h
> @@ -656,6 +656,9 @@
> /*        Ethernet Unit Registers       */
> /****************************************/
>
> +#define MV64340_ETH_PHY_ADDR                                        0x2000
> +#define MV64340_ETH_SMI                                             0x2004
> +
> /*******************************************/
> /*          CUNIT  Registers               */
> /*******************************************/
>
BALATON Zoltan June 21, 2023, 12:34 p.m. UTC | #2
On Wed, 14 Jun 2023, BALATON Zoltan wrote:
> On Mon, 5 Jun 2023, BALATON Zoltan wrote:
>> We don't emulate the gigabit ethernet part of the chip but the MorphOS
>> driver accesses these and expects to get some valid looking result
>> otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
>> 
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> This is only used by MorphOS on pegasos2 so most likely could go via
>> the ppc queue.
>
> Ping?

Ping?

> Regards,
> BALATON Zoltan
>
>> hw/pci-host/mv64361.c | 6 ++++++
>> hw/pci-host/mv643xx.h | 3 +++
>> 2 files changed, 9 insertions(+)
>> 
>> diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
>> index 19e8031a3f..01bd8c887f 100644
>> --- a/hw/pci-host/mv64361.c
>> +++ b/hw/pci-host/mv64361.c
>> @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr 
>> addr, unsigned int size)
>>             }
>>         }
>>         break;
>> +    case MV64340_ETH_PHY_ADDR:
>> +        ret = 0x98;
>> +        break;
>> +    case MV64340_ETH_SMI:
>> +        ret = BIT(27);
>> +        break;
>>     case MV64340_CUNIT_ARBITER_CONTROL_REG:
>>         ret = 0x11ff0000 | (s->gpp_int_level << 10);
>>         break;
>> diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
>> index cd26a43f18..f2e1baea88 100644
>> --- a/hw/pci-host/mv643xx.h
>> +++ b/hw/pci-host/mv643xx.h
>> @@ -656,6 +656,9 @@
>> /*        Ethernet Unit Registers       */
>> /****************************************/
>> 
>> +#define MV64340_ETH_PHY_ADDR                                        0x2000
>> +#define MV64340_ETH_SMI                                             0x2004
>> +
>> /*******************************************/
>> /*          CUNIT  Registers               */
>> /*******************************************/
>> 
>
>
BALATON Zoltan June 29, 2023, 8:36 a.m. UTC | #3
On Wed, 21 Jun 2023, BALATON Zoltan wrote:
> On Wed, 14 Jun 2023, BALATON Zoltan wrote:
>> On Mon, 5 Jun 2023, BALATON Zoltan wrote:
>>> We don't emulate the gigabit ethernet part of the chip but the MorphOS
>>> driver accesses these and expects to get some valid looking result
>>> otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
>>> 
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>> ---
>>> This is only used by MorphOS on pegasos2 so most likely could go via
>>> the ppc queue.
>> 
>> Ping?
>
> Ping?

Ping?
https://patchew.org/QEMU/20230605215145.29458746335@zero.eik.bme.hu/
It's unlikely this will get a review so can you please just merge it? It's 
my code so if I break it I'll fix it but this was tested a bit and no 
problem reported so far.

Regards,
BALATON Zoltan

>>> hw/pci-host/mv64361.c | 6 ++++++
>>> hw/pci-host/mv643xx.h | 3 +++
>>> 2 files changed, 9 insertions(+)
>>> 
>>> diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
>>> index 19e8031a3f..01bd8c887f 100644
>>> --- a/hw/pci-host/mv64361.c
>>> +++ b/hw/pci-host/mv64361.c
>>> @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr 
>>> addr, unsigned int size)
>>>             }
>>>         }
>>>         break;
>>> +    case MV64340_ETH_PHY_ADDR:
>>> +        ret = 0x98;
>>> +        break;
>>> +    case MV64340_ETH_SMI:
>>> +        ret = BIT(27);
>>> +        break;
>>>     case MV64340_CUNIT_ARBITER_CONTROL_REG:
>>>         ret = 0x11ff0000 | (s->gpp_int_level << 10);
>>>         break;
>>> diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
>>> index cd26a43f18..f2e1baea88 100644
>>> --- a/hw/pci-host/mv643xx.h
>>> +++ b/hw/pci-host/mv643xx.h
>>> @@ -656,6 +656,9 @@
>>> /*        Ethernet Unit Registers       */
>>> /****************************************/
>>> 
>>> +#define MV64340_ETH_PHY_ADDR 
>>> 0x2000
>>> +#define MV64340_ETH_SMI 
>>> 0x2004
>>> +
>>> /*******************************************/
>>> /*          CUNIT  Registers               */
>>> /*******************************************/
>>> 
>> 
>> 
>
>
Cédric Le Goater June 29, 2023, 11:04 a.m. UTC | #4
On 6/29/23 10:36, BALATON Zoltan wrote:
> On Wed, 21 Jun 2023, BALATON Zoltan wrote:
>> On Wed, 14 Jun 2023, BALATON Zoltan wrote:
>>> On Mon, 5 Jun 2023, BALATON Zoltan wrote:
>>>> We don't emulate the gigabit ethernet part of the chip but the MorphOS
>>>> driver accesses these and expects to get some valid looking result
>>>> otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
>>>>
>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>> ---
>>>> This is only used by MorphOS on pegasos2 so most likely could go via
>>>> the ppc queue.
>>>
>>> Ping?
>>
>> Ping?
> 
> Ping?
> https://patchew.org/QEMU/20230605215145.29458746335@zero.eik.bme.hu/
> It's unlikely this will get a review so can you please just merge it? It's my code so if I break it I'll fix it but this was tested a bit and no problem reported so far.

Acked-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.

> 
> Regards,
> BALATON Zoltan
> 
>>>> hw/pci-host/mv64361.c | 6 ++++++
>>>> hw/pci-host/mv643xx.h | 3 +++
>>>> 2 files changed, 9 insertions(+)
>>>>
>>>> diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
>>>> index 19e8031a3f..01bd8c887f 100644
>>>> --- a/hw/pci-host/mv64361.c
>>>> +++ b/hw/pci-host/mv64361.c
>>>> @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
>>>>             }
>>>>         }
>>>>         break;
>>>> +    case MV64340_ETH_PHY_ADDR:
>>>> +        ret = 0x98;
>>>> +        break;
>>>> +    case MV64340_ETH_SMI:
>>>> +        ret = BIT(27);
>>>> +        break;
>>>>     case MV64340_CUNIT_ARBITER_CONTROL_REG:
>>>>         ret = 0x11ff0000 | (s->gpp_int_level << 10);
>>>>         break;
>>>> diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
>>>> index cd26a43f18..f2e1baea88 100644
>>>> --- a/hw/pci-host/mv643xx.h
>>>> +++ b/hw/pci-host/mv643xx.h
>>>> @@ -656,6 +656,9 @@
>>>> /*        Ethernet Unit Registers       */
>>>> /****************************************/
>>>>
>>>> +#define MV64340_ETH_PHY_ADDR 0x2000
>>>> +#define MV64340_ETH_SMI 0x2004
>>>> +
>>>> /*******************************************/
>>>> /*          CUNIT  Registers               */
>>>> /*******************************************/
>>>>
>>>
>>>
>>
>>
Daniel Henrique Barboza June 30, 2023, 2:22 p.m. UTC | #5
On 6/29/23 05:36, BALATON Zoltan wrote:
> On Wed, 21 Jun 2023, BALATON Zoltan wrote:
>> On Wed, 14 Jun 2023, BALATON Zoltan wrote:
>>> On Mon, 5 Jun 2023, BALATON Zoltan wrote:
>>>> We don't emulate the gigabit ethernet part of the chip but the MorphOS
>>>> driver accesses these and expects to get some valid looking result
>>>> otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
>>>>
>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>> ---
>>>> This is only used by MorphOS on pegasos2 so most likely could go via
>>>> the ppc queue.
>>>
>>> Ping?
>>
>> Ping?
> 
> Ping?
> https://patchew.org/QEMU/20230605215145.29458746335@zero.eik.bme.hu/
> It's unlikely this will get a review so can you please just merge it? It's my code so if I break it I'll fix it but this was tested a bit and no problem reported so far.
>

Don't worry about it. I'll queue this up.


Daniel

  
> Regards,
> BALATON Zoltan
> 
>>>> hw/pci-host/mv64361.c | 6 ++++++
>>>> hw/pci-host/mv643xx.h | 3 +++
>>>> 2 files changed, 9 insertions(+)
>>>>
>>>> diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
>>>> index 19e8031a3f..01bd8c887f 100644
>>>> --- a/hw/pci-host/mv64361.c
>>>> +++ b/hw/pci-host/mv64361.c
>>>> @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
>>>>             }
>>>>         }
>>>>         break;
>>>> +    case MV64340_ETH_PHY_ADDR:
>>>> +        ret = 0x98;
>>>> +        break;
>>>> +    case MV64340_ETH_SMI:
>>>> +        ret = BIT(27);
>>>> +        break;
>>>>     case MV64340_CUNIT_ARBITER_CONTROL_REG:
>>>>         ret = 0x11ff0000 | (s->gpp_int_level << 10);
>>>>         break;
>>>> diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
>>>> index cd26a43f18..f2e1baea88 100644
>>>> --- a/hw/pci-host/mv643xx.h
>>>> +++ b/hw/pci-host/mv643xx.h
>>>> @@ -656,6 +656,9 @@
>>>> /*        Ethernet Unit Registers       */
>>>> /****************************************/
>>>>
>>>> +#define MV64340_ETH_PHY_ADDR 0x2000
>>>> +#define MV64340_ETH_SMI 0x2004
>>>> +
>>>> /*******************************************/
>>>> /*          CUNIT  Registers               */
>>>> /*******************************************/
>>>>
>>>
>>>
>>
>>
Daniel Henrique Barboza June 30, 2023, 4:44 p.m. UTC | #6
On 6/14/23 16:21, BALATON Zoltan wrote:
> On Mon, 5 Jun 2023, BALATON Zoltan wrote:
>> We don't emulate the gigabit ethernet part of the chip but the MorphOS
>> driver accesses these and expects to get some valid looking result
>> otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> This is only used by MorphOS on pegasos2 so most likely could go via
>> the ppc queue.

And it will.

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel


> 
> Ping?
> 
> Regards,
> BALATON Zoltan
> 
>> hw/pci-host/mv64361.c | 6 ++++++
>> hw/pci-host/mv643xx.h | 3 +++
>> 2 files changed, 9 insertions(+)
>>
>> diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
>> index 19e8031a3f..01bd8c887f 100644
>> --- a/hw/pci-host/mv64361.c
>> +++ b/hw/pci-host/mv64361.c
>> @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
>>             }
>>         }
>>         break;
>> +    case MV64340_ETH_PHY_ADDR:
>> +        ret = 0x98;
>> +        break;
>> +    case MV64340_ETH_SMI:
>> +        ret = BIT(27);
>> +        break;
>>     case MV64340_CUNIT_ARBITER_CONTROL_REG:
>>         ret = 0x11ff0000 | (s->gpp_int_level << 10);
>>         break;
>> diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
>> index cd26a43f18..f2e1baea88 100644
>> --- a/hw/pci-host/mv643xx.h
>> +++ b/hw/pci-host/mv643xx.h
>> @@ -656,6 +656,9 @@
>> /*        Ethernet Unit Registers       */
>> /****************************************/
>>
>> +#define MV64340_ETH_PHY_ADDR                                        0x2000
>> +#define MV64340_ETH_SMI                                             0x2004
>> +
>> /*******************************************/
>> /*          CUNIT  Registers               */
>> /*******************************************/
>>
diff mbox series

Patch

diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
index 19e8031a3f..01bd8c887f 100644
--- a/hw/pci-host/mv64361.c
+++ b/hw/pci-host/mv64361.c
@@ -541,6 +541,12 @@  static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
             }
         }
         break;
+    case MV64340_ETH_PHY_ADDR:
+        ret = 0x98;
+        break;
+    case MV64340_ETH_SMI:
+        ret = BIT(27);
+        break;
     case MV64340_CUNIT_ARBITER_CONTROL_REG:
         ret = 0x11ff0000 | (s->gpp_int_level << 10);
         break;
diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
index cd26a43f18..f2e1baea88 100644
--- a/hw/pci-host/mv643xx.h
+++ b/hw/pci-host/mv643xx.h
@@ -656,6 +656,9 @@ 
 /*        Ethernet Unit Registers       */
 /****************************************/
 
+#define MV64340_ETH_PHY_ADDR                                        0x2000
+#define MV64340_ETH_SMI                                             0x2004
+
 /*******************************************/
 /*          CUNIT  Registers               */
 /*******************************************/