diff mbox series

[v3,12/48] target/arm: Fix test of TCG_OVERSIZED_GUEST

Message ID 20230531040330.8950-13-richard.henderson@linaro.org
State New
Headers show
Series tcg: Build once for system, once for user | expand

Commit Message

Richard Henderson May 31, 2023, 4:02 a.m. UTC
The symbol is always defined, even if to 0.
We wanted to test for TCG_OVERSIZED_GUEST == 0.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/ptw.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Philippe Mathieu-Daudé June 1, 2023, 8:13 p.m. UTC | #1
On 31/5/23 06:02, Richard Henderson wrote:
> The symbol is always defined, even if to 0.
> We wanted to test for TCG_OVERSIZED_GUEST == 0.

Fixes: 71943a1e90 ("target/arm: Implement FEAT_HAFDBS, access flag portion")

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/arm/ptw.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/ptw.c b/target/arm/ptw.c
> index 69c05cd9da..b0d2a05403 100644
> --- a/target/arm/ptw.c
> +++ b/target/arm/ptw.c
> @@ -418,6 +418,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
>                                uint64_t new_val, S1Translate *ptw,
>                                ARMMMUFaultInfo *fi)
>   {
> +#ifdef TARGET_AARCH64

This change ^ ...

>       uint64_t cur_val;
>       void *host = ptw->out_host;
>   
> @@ -473,7 +474,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
>        * we know that TCG_OVERSIZED_GUEST is set, which means that we are
>        * running in round-robin mode and could only race with dma i/o.
>        */
> -#ifndef TCG_OVERSIZED_GUEST
> +#if !TCG_OVERSIZED_GUEST
>   # error "Unexpected configuration"
>   #endif
>       bool locked = qemu_mutex_iothread_locked();
> @@ -497,6 +498,10 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
>   #endif
>   
>       return cur_val;
> +#else
> +    /* AArch32 does not have FEAT_HADFS. */
> +    g_assert_not_reached();

... isn't documented. Do you mind adding a quick line about it?

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> +#endif
>   }
>   
>   static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
diff mbox series

Patch

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 69c05cd9da..b0d2a05403 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -418,6 +418,7 @@  static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
                              uint64_t new_val, S1Translate *ptw,
                              ARMMMUFaultInfo *fi)
 {
+#ifdef TARGET_AARCH64
     uint64_t cur_val;
     void *host = ptw->out_host;
 
@@ -473,7 +474,7 @@  static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
      * we know that TCG_OVERSIZED_GUEST is set, which means that we are
      * running in round-robin mode and could only race with dma i/o.
      */
-#ifndef TCG_OVERSIZED_GUEST
+#if !TCG_OVERSIZED_GUEST
 # error "Unexpected configuration"
 #endif
     bool locked = qemu_mutex_iothread_locked();
@@ -497,6 +498,10 @@  static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
 #endif
 
     return cur_val;
+#else
+    /* AArch32 does not have FEAT_HADFS. */
+    g_assert_not_reached();
+#endif
 }
 
 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,