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([157.82.204.253]) by smtp.gmail.com with ESMTPSA id o10-20020a17090aac0a00b002467717fa60sm4769847pjq.16.2023.05.22.19.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 19:45:48 -0700 (PDT) From: Akihiko Odaki To: Cc: Sriram Yagnaraman , Jason Wang , Dmitry Fleytman , "Michael S . Tsirkin" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Thomas Huth , Wainer dos Santos Moschetta , Beraldo Leal , Cleber Rosa , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, Tomasz Dzieciol , Akihiko Odaki Subject: [PATCH v5 34/48] igb: Implement MSI-X single vector mode Date: Tue, 23 May 2023 11:43:25 +0900 Message-Id: <20230523024339.50875-35-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230523024339.50875-1-akihiko.odaki@daynix.com> References: <20230523024339.50875-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Akihiko Odaki Reviewed-by: Sriram Yagnaraman --- hw/net/igb_core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index c954369964..6d55b43fb4 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1873,7 +1873,7 @@ igb_update_interrupt_state(IGBCore *core) icr = core->mac[ICR] & core->mac[IMS]; - if (msix_enabled(core->owner)) { + if (core->mac[GPIE] & E1000_GPIE_MSIX_MODE) { if (icr) { causes = 0; if (icr & E1000_ICR_DRSTA) { @@ -1908,7 +1908,12 @@ igb_update_interrupt_state(IGBCore *core) trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], core->mac[ICR], core->mac[IMS]); - if (msi_enabled(core->owner)) { + if (msix_enabled(core->owner)) { + if (icr) { + trace_e1000e_irq_msix_notify_vec(0); + msix_notify(core->owner, 0); + } + } else if (msi_enabled(core->owner)) { if (icr) { msi_notify(core->owner, 0); }