From patchwork Fri May 5 01:02:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1777284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=cFO9e48j; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4QCCSd2PKQz214J for ; Fri, 5 May 2023 11:16:33 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujtj-0003Lk-9Z; Thu, 04 May 2023 21:06:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtg-000315-NX for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:08 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujte-0007eu-KV for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:08 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1a516fb6523so10671365ad.3 for ; Thu, 04 May 2023 18:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248765; x=1685840765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j0qdCGr5H/dXi5GZTnoaSiKG2ZdRv1O4vEZjYe7CLHE=; b=cFO9e48jajhGg8KVjk2iedPjaw20Fzq5tKRO0qLdEzcontK7B3NpD498m4CAo8/OeB On8EJS28b/ea+qpACoVsBxIzWHojAY+HPJWk0TxCIWYXxvl/oCDBvKZRDutZP/ra3GdB ebg737vJzMsBnuDJz0wY2+e7PrbbAwmgW7i3b72gSX1ad14Omgjpp9vGGO+lzSv92zi9 dsAuyCFmFOxbVa0qgMBxMQzAZ5uhWs4IZ+WREoWjmTT+f1KTOVb2f97GQTKJjqDkryP6 +1xw3H15VtvPTuuLnIzEcoAMF9A/hVCfuSyNOhcKp0SN+gsJ89/MP0+az3ftywt/Ezru 1RJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248765; x=1685840765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j0qdCGr5H/dXi5GZTnoaSiKG2ZdRv1O4vEZjYe7CLHE=; b=JwiBvuCYuxv79fyv/C9GMzHl2853wt65yUn+j/p9AuK/Wo57lByXRAJII3nWErrOO9 ArtlprZuGX2au+HDgd/opK27/aC60FmchxLHJ9rtV4I/O6hDDHEmG7ZRxRK3hLTGKOhO +3aHr7kdl7QXt+9UbWKJjgAlwBMiGt8XFt7VxMCKN8xsQr5vnDSNErQVa56CN9K4GV+K SdQ0E+A1aFuXXF0S/bBmRFBZXNznzsWfS6vT8KNQkgLE+ERmFp0SlR6+8qL0F2cUkNLy s8bw2FBxYH989ECVtUuKRF8SP2xPvOPZw1qROE+GwyMLrgyCH2LricrXvZN69vlOrsGC Z2gA== X-Gm-Message-State: AC+VfDxNjAlg6gMmhN+wTvciboUHMCXZyxXad25tGYsb6z9c9zBLlGQ2 /lSUMGsVLuBrlqLypQRBymoor1cghtQL6Q== X-Google-Smtp-Source: ACHHUZ7XSfKzqvHa0j/ucS/pAnDOV5zUEZxCTfo8UwZ1Xj8N5vwL04dWfBoYbDocMXwqWOc8oBsxqQ== X-Received: by 2002:a17:903:187:b0:1a8:1320:133 with SMTP id z7-20020a170903018700b001a813200133mr6530699plg.51.1683248764870; Thu, 04 May 2023 18:06:04 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Date: Fri, 5 May 2023 11:02:01 +1000 Message-Id: <20230505010241.21812-50-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Daniel Henrique Barboza This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an existing MISA bit (cfg.ext_g will be handled shortly). The function is now a no-op, simply copying the existing values of misa_ext* back to misa_ext*. Remove it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 52 ---------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13ff37250e..1ecb82bb5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1141,50 +1141,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) #endif } -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) -{ - uint32_t ext = 0; - - if (riscv_has_ext(env, RVI)) { - ext |= RVI; - } - if (riscv_has_ext(env, RVE)) { - ext |= RVE; - } - if (riscv_has_ext(env, RVM)) { - ext |= RVM; - } - if (riscv_has_ext(env, RVA)) { - ext |= RVA; - } - if (riscv_has_ext(env, RVF)) { - ext |= RVF; - } - if (riscv_has_ext(env, RVD)) { - ext |= RVD; - } - if (riscv_has_ext(env, RVC)) { - ext |= RVC; - } - if (riscv_has_ext(env, RVS)) { - ext |= RVS; - } - if (riscv_has_ext(env, RVU)) { - ext |= RVU; - } - if (riscv_has_ext(env, RVH)) { - ext |= RVH; - } - if (riscv_has_ext(env, RVV)) { - ext |= RVV; - } - if (riscv_has_ext(env, RVJ)) { - ext |= RVJ; - } - - env->misa_ext = env->misa_ext_mask = ext; -} - static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -1228,14 +1184,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); } - /* - * We can't be sure of whether we set defaults during cpu_init() - * or whether the user enabled/disabled some bits via cpu->cfg - * flags. Sync env->misa_ext with cpu->cfg now to allow us to - * use just env->misa_ext later. - */ - riscv_cpu_sync_misa_cfg(env); - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err != NULL) { error_propagate(errp, local_err);