diff mbox series

[v4,45/48] igb: Clear-on-read ICR when ICR.INTA is set

Message ID 20230426103716.26279-46-akihiko.odaki@daynix.com
State New
Headers show
Series igb: Fix for DPDK | expand

Commit Message

Akihiko Odaki April 26, 2023, 10:37 a.m. UTC 
For GPIE.NSICR, Section 7.3.2.1.2 says:
> ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> clear on read occurs only if no bit is set in the IMS or at least one
> bit is set in the IMS and there is a true interrupt as reflected in
> ICR.INTA.

e1000e does similar though it checks for CTRL_EXT.IAME, which does not
exist on igb.

Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
 hw/net/igb_core.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Sriram Yagnaraman April 26, 2023, 12:39 p.m. UTC | #1 
> -----Original Message-----
> From: Akihiko Odaki <akihiko.odaki@daynix.com>
> Sent: Wednesday, 26 April 2023 12:37
> Cc: Sriram Yagnaraman <sriram.yagnaraman@est.tech>; Jason Wang
> <jasowang@redhat.com>; Dmitry Fleytman <dmitry.fleytman@gmail.com>;
> Michael S . Tsirkin <mst@redhat.com>; Alex Bennée
> <alex.bennee@linaro.org>; Philippe Mathieu-Daudé <philmd@linaro.org>;
> Thomas Huth <thuth@redhat.com>; Wainer dos Santos Moschetta
> <wainersm@redhat.com>; Beraldo Leal <bleal@redhat.com>; Cleber Rosa
> <crosa@redhat.com>; Laurent Vivier <lvivier@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; qemu-devel@nongnu.org; Tomasz Dzieciol
> <t.dzieciol@partner.samsung.com>; Akihiko Odaki
> <akihiko.odaki@daynix.com>
> Subject: [PATCH v4 45/48] igb: Clear-on-read ICR when ICR.INTA is set
> 
> For GPIE.NSICR, Section 7.3.2.1.2 says:
> > ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> > clear on read occurs only if no bit is set in the IMS or at least one
> > bit is set in the IMS and there is a true interrupt as reflected in
> > ICR.INTA.
> 
> e1000e does similar though it checks for CTRL_EXT.IAME, which does not exist
> on igb.
> 
> Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
> ---
>  hw/net/igb_core.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index
> b68e24c9ee..29190054c6 100644
> --- a/hw/net/igb_core.c
> +++ b/hw/net/igb_core.c
> @@ -2598,6 +2598,8 @@ igb_mac_icr_read(IGBCore *core, int index)
>      } else if (core->mac[IMS] == 0) {
>          trace_e1000e_irq_icr_clear_zero_ims();
>          igb_lower_interrupts(core, ICR, 0xffffffff);
> +    } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) {
> +        igb_lower_interrupts(core, ICR, 0xffffffff);
>      } else if (!msix_enabled(core->owner)) {
>          trace_e1000e_irq_icr_clear_nonmsix_icr_read();
>          igb_lower_interrupts(core, ICR, 0xffffffff);
> --
> 2.40.0

Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
diff mbox series

Patch

diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index b68e24c9ee..29190054c6 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -2598,6 +2598,8 @@  igb_mac_icr_read(IGBCore *core, int index)
     } else if (core->mac[IMS] == 0) {
         trace_e1000e_irq_icr_clear_zero_ims();
         igb_lower_interrupts(core, ICR, 0xffffffff);
+    } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) {
+        igb_lower_interrupts(core, ICR, 0xffffffff);
     } else if (!msix_enabled(core->owner)) {
         trace_e1000e_irq_icr_clear_nonmsix_icr_read();
         igb_lower_interrupts(core, ICR, 0xffffffff);