Message ID | 20230418123624.16414-1-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | target/riscv: add Ventana's Veyron V1 CPU | expand |
On Tue, Apr 18, 2023 at 10:37 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > From: Rahul Pathak <rpathak@ventanamicro.com> > > Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs > exclusively for the rv64 target. It's tested with the 'virt' board. > > CPU specs and general information can be found here: > > https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/ > > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++ > target/riscv/cpu_vendorid.h | 4 ++++ > 3 files changed, 43 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index b29090ad86..04af50983e 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -41,6 +41,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") > +#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #if defined(TARGET_RISCV32) > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index befa64528f..db0875fb43 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -422,6 +422,43 @@ static void rv64_thead_c906_cpu_init(Object *obj) > #endif > } > > +static void rv64_veyron_v1_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); > + env->priv_ver = PRIV_VERSION_1_12_0; > + > + /* Enable ISA extensions */ > + cpu->cfg.mmu = true; > + cpu->cfg.ext_icbom = true; > + cpu->cfg.cbom_blocksize = 64; > + cpu->cfg.cboz_blocksize = 64; > + cpu->cfg.ext_icboz = true; > + cpu->cfg.ext_smaia = true; > + cpu->cfg.ext_ssaia = true; > + cpu->cfg.ext_sscofpmf = true; > + cpu->cfg.ext_sstc = true; > + cpu->cfg.ext_svinval = true; > + cpu->cfg.ext_svnapot = true; > + cpu->cfg.ext_svpbmt = true; > + cpu->cfg.ext_smstateen = true; > + cpu->cfg.ext_zba = true; > + cpu->cfg.ext_zbb = true; > + cpu->cfg.ext_zbc = true; > + cpu->cfg.ext_zbs = true; > + cpu->cfg.ext_XVentanaCondOps = true; > + > + cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; > + cpu->cfg.marchid = VEYRON_V1_MARCHID; > + cpu->cfg.mimpid = VEYRON_V1_MIMPID; > + > +#ifndef CONFIG_USER_ONLY > + set_satp_mode_max_supported(cpu, VM_1_10_SV48); > +#endif > +} > + > static void rv128_base_cpu_init(Object *obj) > { > if (qemu_tcg_mttcg_enabled()) { > @@ -1827,6 +1864,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), > #endif > }; > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h > index a5aa249bc9..96b6b9c2cb 100644 > --- a/target/riscv/cpu_vendorid.h > +++ b/target/riscv/cpu_vendorid.h > @@ -3,4 +3,8 @@ > > #define THEAD_VENDOR_ID 0x5b7 > > +#define VEYRON_V1_MARCHID 0x8000000000010000 > +#define VEYRON_V1_MIMPID 0x111 > +#define VEYRON_V1_MVENDORID 0x61f > + > #endif /* TARGET_RISCV_CPU_VENDORID_H */ > -- > 2.40.0 > >
On Tue, Apr 18, 2023 at 10:37 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > From: Rahul Pathak <rpathak@ventanamicro.com> > > Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs > exclusively for the rv64 target. It's tested with the 'virt' board. > > CPU specs and general information can be found here: > > https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/ > > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++ > target/riscv/cpu_vendorid.h | 4 ++++ > 3 files changed, 43 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index b29090ad86..04af50983e 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -41,6 +41,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") > +#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #if defined(TARGET_RISCV32) > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index befa64528f..db0875fb43 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -422,6 +422,43 @@ static void rv64_thead_c906_cpu_init(Object *obj) > #endif > } > > +static void rv64_veyron_v1_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); > + env->priv_ver = PRIV_VERSION_1_12_0; > + > + /* Enable ISA extensions */ > + cpu->cfg.mmu = true; > + cpu->cfg.ext_icbom = true; > + cpu->cfg.cbom_blocksize = 64; > + cpu->cfg.cboz_blocksize = 64; > + cpu->cfg.ext_icboz = true; > + cpu->cfg.ext_smaia = true; > + cpu->cfg.ext_ssaia = true; > + cpu->cfg.ext_sscofpmf = true; > + cpu->cfg.ext_sstc = true; > + cpu->cfg.ext_svinval = true; > + cpu->cfg.ext_svnapot = true; > + cpu->cfg.ext_svpbmt = true; > + cpu->cfg.ext_smstateen = true; > + cpu->cfg.ext_zba = true; > + cpu->cfg.ext_zbb = true; > + cpu->cfg.ext_zbc = true; > + cpu->cfg.ext_zbs = true; > + cpu->cfg.ext_XVentanaCondOps = true; > + > + cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; > + cpu->cfg.marchid = VEYRON_V1_MARCHID; > + cpu->cfg.mimpid = VEYRON_V1_MIMPID; > + > +#ifndef CONFIG_USER_ONLY > + set_satp_mode_max_supported(cpu, VM_1_10_SV48); > +#endif > +} > + > static void rv128_base_cpu_init(Object *obj) > { > if (qemu_tcg_mttcg_enabled()) { > @@ -1827,6 +1864,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), > #endif > }; > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h > index a5aa249bc9..96b6b9c2cb 100644 > --- a/target/riscv/cpu_vendorid.h > +++ b/target/riscv/cpu_vendorid.h > @@ -3,4 +3,8 @@ > > #define THEAD_VENDOR_ID 0x5b7 > > +#define VEYRON_V1_MARCHID 0x8000000000010000 > +#define VEYRON_V1_MIMPID 0x111 > +#define VEYRON_V1_MVENDORID 0x61f > + > #endif /* TARGET_RISCV_CPU_VENDORID_H */ > -- > 2.40.0 > >
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b29090ad86..04af50983e 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -41,6 +41,7 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index befa64528f..db0875fb43 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -422,6 +422,43 @@ static void rv64_thead_c906_cpu_init(Object *obj) #endif } +static void rv64_veyron_v1_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + env->priv_ver = PRIV_VERSION_1_12_0; + + /* Enable ISA extensions */ + cpu->cfg.mmu = true; + cpu->cfg.ext_icbom = true; + cpu->cfg.cbom_blocksize = 64; + cpu->cfg.cboz_blocksize = 64; + cpu->cfg.ext_icboz = true; + cpu->cfg.ext_smaia = true; + cpu->cfg.ext_ssaia = true; + cpu->cfg.ext_sscofpmf = true; + cpu->cfg.ext_sstc = true; + cpu->cfg.ext_svinval = true; + cpu->cfg.ext_svnapot = true; + cpu->cfg.ext_svpbmt = true; + cpu->cfg.ext_smstateen = true; + cpu->cfg.ext_zba = true; + cpu->cfg.ext_zbb = true; + cpu->cfg.ext_zbc = true; + cpu->cfg.ext_zbs = true; + cpu->cfg.ext_XVentanaCondOps = true; + + cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; + cpu->cfg.marchid = VEYRON_V1_MARCHID; + cpu->cfg.mimpid = VEYRON_V1_MIMPID; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV48); +#endif +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1827,6 +1864,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h index a5aa249bc9..96b6b9c2cb 100644 --- a/target/riscv/cpu_vendorid.h +++ b/target/riscv/cpu_vendorid.h @@ -3,4 +3,8 @@ #define THEAD_VENDOR_ID 0x5b7 +#define VEYRON_V1_MARCHID 0x8000000000010000 +#define VEYRON_V1_MIMPID 0x111 +#define VEYRON_V1_MVENDORID 0x61f + #endif /* TARGET_RISCV_CPU_VENDORID_H */