| Message ID | 20230413090122.65228-3-liweiwei@iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Fix PMP related problem | expand |
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > pmp_get_tlb_size have no relationship with pmp-related permission check > currently. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 16 ++++++---------- > 1 file changed, 6 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 075fc0538a..83c9699a6d 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -676,14 +676,11 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) > * > * @env: CPURISCVState > * @prot: The returned protection attributes > - * @tlb_size: TLB page size containing addr. It could be modified after PMP > - * permission checking. NULL if not set TLB page for addr. > * @addr: The physical address to be checked permission > * @access_type: The type of MMU access > * @mode: Indicates current privilege level. > */ > -static int get_physical_address_pmp(CPURISCVState *env, int *prot, > - target_ulong *tlb_size, hwaddr addr, > +static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, > int size, MMUAccessType access_type, > int mode) > { > @@ -703,9 +700,6 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, > } > > *prot = pmp_priv_to_page_prot(pmp_priv); > - if (tlb_size != NULL) { > - *tlb_size = pmp_get_tlb_size(env, addr); > - } > > return TRANSLATE_SUCCESS; > } > @@ -905,7 +899,7 @@ restart: > } > > int pmp_prot; > - int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, > + int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr, > sizeof(target_ulong), > MMU_DATA_LOAD, PRV_S); > if (pmp_ret != TRANSLATE_SUCCESS) { > @@ -1300,8 +1294,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > prot &= prot2; > > if (ret == TRANSLATE_SUCCESS) { > - ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, > + ret = get_physical_address_pmp(env, &prot_pmp, pa, > size, access_type, mode); > + tlb_size = pmp_get_tlb_size(env, pa); > > qemu_log_mask(CPU_LOG_MMU, > "%s PMP address=" HWADDR_FMT_plx " ret %d prot" > @@ -1333,8 +1328,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > __func__, address, ret, pa, prot); > > if (ret == TRANSLATE_SUCCESS) { > - ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, > + ret = get_physical_address_pmp(env, &prot_pmp, pa, > size, access_type, mode); > + tlb_size = pmp_get_tlb_size(env, pa); > > qemu_log_mask(CPU_LOG_MMU, > "%s PMP address=" HWADDR_FMT_plx " ret %d prot" > -- > 2.25.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 075fc0538a..83c9699a6d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -676,14 +676,11 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) * * @env: CPURISCVState * @prot: The returned protection attributes - * @tlb_size: TLB page size containing addr. It could be modified after PMP - * permission checking. NULL if not set TLB page for addr. * @addr: The physical address to be checked permission * @access_type: The type of MMU access * @mode: Indicates current privilege level. */ -static int get_physical_address_pmp(CPURISCVState *env, int *prot, - target_ulong *tlb_size, hwaddr addr, +static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, int size, MMUAccessType access_type, int mode) { @@ -703,9 +700,6 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, } *prot = pmp_priv_to_page_prot(pmp_priv); - if (tlb_size != NULL) { - *tlb_size = pmp_get_tlb_size(env, addr); - } return TRANSLATE_SUCCESS; } @@ -905,7 +899,7 @@ restart: } int pmp_prot; - int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, + int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr, sizeof(target_ulong), MMU_DATA_LOAD, PRV_S); if (pmp_ret != TRANSLATE_SUCCESS) { @@ -1300,8 +1294,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, prot &= prot2; if (ret == TRANSLATE_SUCCESS) { - ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, + ret = get_physical_address_pmp(env, &prot_pmp, pa, size, access_type, mode); + tlb_size = pmp_get_tlb_size(env, pa); qemu_log_mask(CPU_LOG_MMU, "%s PMP address=" HWADDR_FMT_plx " ret %d prot" @@ -1333,8 +1328,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { - ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, + ret = get_physical_address_pmp(env, &prot_pmp, pa, size, access_type, mode); + tlb_size = pmp_get_tlb_size(env, pa); qemu_log_mask(CPU_LOG_MMU, "%s PMP address=" HWADDR_FMT_plx " ret %d prot"