| Message ID | 20230412121829.14452-7-farosas@suse.de |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Allow CONFIG_TCG=n builds | expand |
On 12/4/23 14:18, Fabiano Rosas wrote: > From: Claudio Fontana <cfontana@suse.de> > > move the module containing cpu models definitions > for 32bit TCG-only CPUs to tcg/ and rename it for clarity. > > Signed-off-by: Claudio Fontana <cfontana@suse.de> > Signed-off-by: Fabiano Rosas <farosas@suse.de> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Acked-by: Thomas Huth <thuth@redhat.com> > --- > hw/arm/virt.c | 2 +- > target/arm/meson.build | 1 - > target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++---------- > target/arm/tcg/cpu64.c | 2 +- > target/arm/tcg/meson.build | 1 + > tests/qtest/arm-cpu-features.c | 12 +++++++++--- > 6 files changed, 15 insertions(+), 16 deletions(-) > rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%) > diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c > index 1cb08138ad..1555b0bab8 100644 > --- a/tests/qtest/arm-cpu-features.c > +++ b/tests/qtest/arm-cpu-features.c > @@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void *data) > QDict *resp; > char *error; > > - assert_error(qts, "cortex-a15", > - "We cannot guarantee the CPU type 'cortex-a15' works " > - "with KVM on this host", NULL); > + if (qtest_has_accel("tcg")) { Can we add a comment to explain this non trivial case? I suppose the reason is "KVM is builtin but not available, so we don't want to test the TCG fallback", is that correct? > + assert_error(qts, "cortex-a15", > + "We cannot guarantee the CPU type 'cortex-a15' works " > + "with KVM on this host", NULL); > + } else { > + assert_error(qts, "cortex-a15", > + "The CPU type 'cortex-a15' is not a " > + "recognized ARM CPU type", NULL); > + } > > assert_has_feature_enabled(qts, "host", "aarch64"); >
Philippe Mathieu-Daudé <philmd@linaro.org> writes: > On 12/4/23 14:18, Fabiano Rosas wrote: >> From: Claudio Fontana <cfontana@suse.de> >> >> move the module containing cpu models definitions >> for 32bit TCG-only CPUs to tcg/ and rename it for clarity. >> >> Signed-off-by: Claudio Fontana <cfontana@suse.de> >> Signed-off-by: Fabiano Rosas <farosas@suse.de> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Acked-by: Thomas Huth <thuth@redhat.com> >> --- >> hw/arm/virt.c | 2 +- >> target/arm/meson.build | 1 - >> target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++---------- >> target/arm/tcg/cpu64.c | 2 +- >> target/arm/tcg/meson.build | 1 + >> tests/qtest/arm-cpu-features.c | 12 +++++++++--- >> 6 files changed, 15 insertions(+), 16 deletions(-) >> rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%) > > >> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c >> index 1cb08138ad..1555b0bab8 100644 >> --- a/tests/qtest/arm-cpu-features.c >> +++ b/tests/qtest/arm-cpu-features.c >> @@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void *data) >> QDict *resp; >> char *error; >> >> - assert_error(qts, "cortex-a15", >> - "We cannot guarantee the CPU type 'cortex-a15' works " >> - "with KVM on this host", NULL); >> + if (qtest_has_accel("tcg")) { > > Can we add a comment to explain this non trivial case? > Hi, good idea, this is a bit opaque indeed. > I suppose the reason is "KVM is builtin but not available, so we don't > want to test the TCG fallback", is that correct? > No, it's just that originally the default cpu was cortex-a15 which we don't give guarantees for when using KVM. But now that cpu is not present in the KVM-only build at all, hence "The CPU ... is not a recognized ARM CPU type". >> + assert_error(qts, "cortex-a15", >> + "We cannot guarantee the CPU type 'cortex-a15' works " >> + "with KVM on this host", NULL); >> + } else { >> + assert_error(qts, "cortex-a15", >> + "The CPU type 'cortex-a15' is not a " >> + "recognized ARM CPU type", NULL); >> + } >> >> assert_has_feature_enabled(qts, "host", "aarch64"); >>
diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 999c1ada79..b661b8d91b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,9 +204,9 @@ static const int a15irqmap[] = { }; static const char *valid_cpus[] = { +#ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a7"), ARM_CPU_TYPE_NAME("cortex-a15"), -#ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a55"), ARM_CPU_TYPE_NAME("cortex-a72"), diff --git a/target/arm/meson.build b/target/arm/meson.build index 3469926295..359a649eaf 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,7 +5,6 @@ arm_ss.add(files( 'gdbstub.c', 'helper.c', 'vfp_helper.c', - 'cpu_tcg.c', )) arm_ss.add(zlib) diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/cpu32.c similarity index 99% rename from target/arm/cpu_tcg.c rename to target/arm/tcg/cpu32.c index 6ce728134f..a03c819b41 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/tcg/cpu32.c @@ -1,5 +1,5 @@ /* - * QEMU ARM TCG CPUs. + * QEMU ARM TCG-only CPUs. * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -10,9 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -#endif /* CONFIG_TCG */ #include "internals.h" #include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) @@ -96,7 +94,7 @@ void aa32_max_features(ARMCPU *cpu) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#if !defined(CONFIG_USER_ONLY) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -120,7 +118,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return ret; } -#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ static void arm926_initfn(Object *obj) { @@ -1016,7 +1014,6 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } -#ifdef CONFIG_TCG static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, @@ -1037,7 +1034,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { .debug_check_breakpoint = arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; -#endif /* CONFIG_TCG */ static void arm_v7m_class_init(ObjectClass *oc, void *data) { @@ -1045,10 +1041,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) CPUClass *cc = CPU_CLASS(oc); acc->info = data; -#ifdef CONFIG_TCG cc->tcg_ops = &arm_v7m_tcg_ops; -#endif /* CONFIG_TCG */ - cc->gdb_core_xml_file = "arm-m-profile.xml"; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index f65b52fb76..8e6d50dc5c 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -525,7 +525,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) /* * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c; + * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; * this only needs to handle 64 bits. */ void aarch64_max_tcg_initfn(Object *obj) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 128f782816..4d99f6dacb 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -18,6 +18,7 @@ gen = [ arm_ss.add(gen) arm_ss.add(files( + 'cpu32.c', 'translate.c', 'translate-m-nocp.c', 'translate-mve.c', diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 1cb08138ad..1555b0bab8 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void *data) QDict *resp; char *error; - assert_error(qts, "cortex-a15", - "We cannot guarantee the CPU type 'cortex-a15' works " - "with KVM on this host", NULL); + if (qtest_has_accel("tcg")) { + assert_error(qts, "cortex-a15", + "We cannot guarantee the CPU type 'cortex-a15' works " + "with KVM on this host", NULL); + } else { + assert_error(qts, "cortex-a15", + "The CPU type 'cortex-a15' is not a " + "recognized ARM CPU type", NULL); + } assert_has_feature_enabled(qts, "host", "aarch64");