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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv Date: Wed, 12 Apr 2023 13:43:23 +0200 Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 10 +--------- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfd1d739b..ccba3c45e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage == false) { /* * We are in stage 2 translation, this is similar to stage 1. @@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode == PRV_M && access_type != MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index a5de3daee7..49c19d971d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)