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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:05:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 20/20] target/riscv/cpu.c: redesign register_cpu_props() Date: Thu, 6 Apr 2023 15:03:51 -0300 Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user properties to set/remove CPU extensions. Make a note that it will overwrite env->misa_ext with the defaults set by each user property. Update the MISA bits comment in cpu.h as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 41 ++++++++++------------------------------- target/riscv/cpu.h | 5 +---- 2 files changed, 11 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 143079a8df..d1769fd218 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -228,7 +228,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(Object *obj); +static void riscv_cpu_add_user_properties(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -356,7 +356,6 @@ static void riscv_any_cpu_init(Object *obj) #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -365,7 +364,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -377,7 +376,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -390,7 +388,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY @@ -436,7 +433,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -449,7 +446,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -461,7 +458,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -474,7 +470,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY @@ -488,7 +483,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY @@ -503,7 +497,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY @@ -521,7 +514,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); } #endif @@ -1577,30 +1570,16 @@ static Property riscv_cpu_extensions[] = { }; /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext = 0 means that we want - * all the default properties to be registered. + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). */ -static void register_cpu_props(Object *obj) +static void riscv_cpu_add_user_properties(Object *obj) { - RISCVCPU *cpu = RISCV_CPU(obj); Property *prop; DeviceState *dev = DEVICE(obj); - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext != 0) { - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - riscv_cpu_add_misa_properties(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 070547234b..f47c3fc139 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,10 +65,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) -/* - * Consider updating register_cpu_props() when adding - * new MISA bits here. - */ +/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M')