@@ -402,7 +402,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.ext_g = true;
cpu->cfg.ext_u = true;
- cpu->cfg.ext_s = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
@@ -837,7 +836,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+ if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
@@ -849,7 +848,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
+ if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
@@ -1109,7 +1108,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVC)) {
ext |= RVC;
}
- if (riscv_cpu_cfg(env)->ext_s) {
+ if (riscv_has_ext(env, RVS)) {
ext |= RVS;
}
if (riscv_cpu_cfg(env)->ext_u) {
@@ -1448,6 +1447,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVE, .enabled = false},
{.name = "m", .description = "Integer multiplication and division",
.misa_bit = RVM, .enabled = true},
+ {.name = "s", .description = "Supervisor-level instructions",
+ .misa_bit = RVS, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1471,7 +1472,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
@@ -1579,7 +1579,6 @@ static void register_cpu_props(Object *obj)
*/
if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_v = misa_ext & RVV;
- cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;
cpu->cfg.ext_j = misa_ext & RVJ;
@@ -419,7 +419,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_s;
bool ext_u;
bool ext_h;
bool ext_j;
Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 11 +++++------ target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 7 deletions(-)