| Message ID | 20230322222004.357013-15-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: rework CPU extensions validation | expand |
On 2023/3/23 06:19, Daniel Henrique Barboza wrote: > The 'G' bit in misa_ext is a virtual extension that enables a set of > extensions (i, m, a, f, d, icsr and ifencei). We're already have code to > handle it but no bit definition. Add it. > > Add RVG to set_misa() in rv64_thead_c906_cpu_init() and remove the > manual cpu->cfg.ext_g assignment while we're at it. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 8 ++++++-- > target/riscv/cpu.h | 1 + > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c4f18d0436..f41888baa0 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -274,6 +274,9 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) > if (cfg->ext_j) { > ext |= RVJ; > } > + if (cfg->ext_g) { > + ext |= RVG; > + } > > return ext; > } > @@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, > cfg->ext_u = misa_ext & RVU; > cfg->ext_h = misa_ext & RVH; > cfg->ext_j = misa_ext & RVJ; > + cfg->ext_g = misa_ext & RVG; > } > > static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) > @@ -474,10 +478,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > RISCVCPU *cpu = RISCV_CPU(obj); > > - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | > + RVC | RVS | RVU | RVG); > env->priv_ver = PRIV_VERSION_1_11_0; > > - cpu->cfg.ext_g = true; > cpu->cfg.ext_icsr = true; Assignment for ext_icsr and ext_ifencei also can be deleted when RVG is set. Regards, Weiwei Li > cpu->cfg.ext_zfh = true; > cpu->cfg.mmu = true; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 2263629332..dbb4df9df0 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -82,6 +82,7 @@ > #define RVU RV('U') > #define RVH RV('H') > #define RVJ RV('J') > +#define RVG RV('G') > > > /* Privileged specification version */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c4f18d0436..f41888baa0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,6 +274,9 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) if (cfg->ext_j) { ext |= RVJ; } + if (cfg->ext_g) { + ext |= RVG; + } return ext; } @@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, cfg->ext_u = misa_ext & RVU; cfg->ext_h = misa_ext & RVH; cfg->ext_j = misa_ext & RVJ; + cfg->ext_g = misa_ext & RVG; } static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) @@ -474,10 +478,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | + RVC | RVS | RVU | RVG); env->priv_ver = PRIV_VERSION_1_11_0; - cpu->cfg.ext_g = true; cpu->cfg.ext_icsr = true; cpu->cfg.ext_zfh = true; cpu->cfg.mmu = true; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2263629332..dbb4df9df0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') /* Privileged specification version */
The 'G' bit in misa_ext is a virtual extension that enables a set of extensions (i, m, a, f, d, icsr and ifencei). We're already have code to handle it but no bit definition. Add it. Add RVG to set_misa() in rv64_thead_c906_cpu_init() and remove the manual cpu->cfg.ext_g assignment while we're at it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 8 ++++++-- target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-)