@@ -939,7 +939,8 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
-static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+static void riscv_cpu_validate_v(CPURISCVState *env,
+ const RISCVCPUConfig *cfg,
Error **errp)
{
int vext_version = VEXT_VERSION_1_00_0;
@@ -1025,46 +1026,48 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
}
}
-static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp)
+
+static void riscv_cpu_validate_misa_ext(CPURISCVState *env,
+ uint32_t misa_ext,
+ Error **errp)
{
- CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
- if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+ if (misa_ext & RVI && misa_ext & RVE) {
error_setg(errp,
"I and E extensions are incompatible");
return;
}
- if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+ if (!(misa_ext & RVI) && !(misa_ext & RVE)) {
error_setg(errp,
"Either I or E extension must be set");
return;
}
- if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+ if (misa_ext & RVS && !(misa_ext & RVU)) {
error_setg(errp,
"Setting S extension without U extension is illegal");
return;
}
- if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+ if (misa_ext & RVH && !(misa_ext & RVI)) {
error_setg(errp,
"H depends on an I base integer ISA with 32 x registers");
return;
}
- if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
+ if (misa_ext & RVH && !(misa_ext & RVS)) {
error_setg(errp, "H extension implicitly requires S-mode");
return;
}
- if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
+ if (misa_ext & RVD && !(misa_ext & RVF)) {
error_setg(errp, "D extension requires F extension");
return;
}
- if (cpu->cfg.ext_v) {
+ if (misa_ext & RVV) {
/*
* V depends on Zve64d, which requires D. It also
* depends on Zve64f, which depends on Zve32f,
@@ -1072,12 +1075,12 @@ static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp)
*
* This means that V depends on both D and F.
*/
- if (!(cpu->cfg.ext_d && cpu->cfg.ext_f)) {
+ if (!(misa_ext & RVD && misa_ext & RVF)) {
error_setg(errp, "V extension requires D and F extensions");
return;
}
- riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+ riscv_cpu_validate_v(env, riscv_cpu_cfg(env), &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
@@ -1331,6 +1334,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPUState *cs = CPU(dev);
RISCVCPU *cpu = RISCV_CPU(dev);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+ CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -1355,7 +1359,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_set_G_virt_ext(cpu);
}
- riscv_cpu_validate_misa_ext(cpu, &local_err);
+ riscv_cpu_validate_misa_ext(env, env->misa_ext, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
We have all MISA specific validations in riscv_cpu_validate_misa_ext(), and we have a guarantee that env->misa_ext will always be in sync with cpu->cfg at this point during realize time, so let's convert it to use a 'misa_ext' parameter instead of reading cpu->cfg. This will prepare the function to be used in write_misa() where we won't have an updated cpu->cfg object to work with. riscv_cpu_validate_v() is changed to receive a const pointer to the cpu->cfg object via riscv_cpu_cfg(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-)