diff mbox series

[PULL,24/67] target/loongarch: Remove `NB_MMU_MODES` define

Message ID	20230307175848.2508955-25-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Anton Johansson <anjo@rev.ng>, =?utf-8?q?Phili?= =?utf-8?q?ppe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= <alex.bennee@linaro.org> Subject: [PULL 24/67] target/loongarch: Remove `NB_MMU_MODES` define Date: Tue, 7 Mar 2023 09:58:05 -0800 Message-Id: <20230307175848.2508955-25-richard.henderson@linaro.org> In-Reply-To: <20230307175848.2508955-1-richard.henderson@linaro.org> References: <20230307175848.2508955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/67] target/mips: Drop tcg_temp_free from micromips_translate.c.inc \| expand [PULL,01/67] target/mips: Drop tcg_temp_free from micromips_translate.c.inc [PULL,02/67] target/mips: Drop tcg_temp_free from msa_translate.c [PULL,03/67] target/mips: Drop tcg_temp_free from mxu_translate.c [PULL,04/67] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc [PULL,05/67] target/mips: Drop tcg_temp_free from octeon_translate.c [PULL,06/67] target/mips: Drop tcg_temp_free from translate_addr_const.c [PULL,07/67] target/mips: Drop tcg_temp_free from tx79_translate.c [PULL,08/67] target/mips: Drop tcg_temp_free from vr54xx_translate.c [PULL,09/67] target/mips: Drop tcg_temp_free from translate.c [PULL,10/67] target/s390x: Drop free_compare [PULL,11/67] target/s390x: Drop tcg_temp_free from translate_vx.c.inc [PULL,12/67] target/s390x: Drop tcg_temp_free from translate.c [PULL,13/67] target/s390x: Remove assert vs g_in2 [PULL,14/67] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext [PULL,15/67] tcg: Create tcg/tcg-temp-internal.h [PULL,16/67] include/exec: Set default `NB_MMU_MODES` to 16 [PULL,17/67] target/alpha: Remove `NB_MMU_MODES` define [PULL,18/67] target/arm: Remove `NB_MMU_MODES` define [PULL,19/67] target/avr: Remove `NB_MMU_MODES` define [PULL,20/67] target/cris: Remove `NB_MMU_MODES` define [PULL,21/67] target/hexagon: Remove `NB_MMU_MODES` define [PULL,22/67] target/hppa: Remove `NB_MMU_MODES` define [PULL,23/67] target/i386: Remove `NB_MMU_MODES` define [PULL,24/67] target/loongarch: Remove `NB_MMU_MODES` define [PULL,25/67] target/m68k: Remove `NB_MMU_MODES` define [PULL,26/67] target/microblaze: Remove `NB_MMU_MODES` define [PULL,27/67] target/mips: Remove `NB_MMU_MODES` define [PULL,28/67] target/nios2: Remove `NB_MMU_MODES` define [PULL,29/67] target/openrisc: Remove `NB_MMU_MODES` define [PULL,30/67] target/ppc: Remove `NB_MMU_MODES` define [PULL,31/67] target/riscv: Remove `NB_MMU_MODES` define [PULL,32/67] target/rx: Remove `NB_MMU_MODES` define [PULL,33/67] target/s390x: Remove `NB_MMU_MODES` define [PULL,34/67] target/sh4: Remove `NB_MMU_MODES` define [PULL,35/67] target/sparc: Remove `NB_MMU_MODES` define [PULL,36/67] target/tricore: Remove `NB_MMU_MODES` define [PULL,37/67] target/xtensa: Remove `NB_MMU_MODES` define [PULL,38/67] include/exec: Remove guards around `NB_MMU_MODES` [PULL,39/67] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS [PULL,40/67] target/avr: Avoid use of tcg_const_i32 throughout [PULL,41/67] target/cris: Avoid use of tcg_const_i32 throughout [PULL,42/67] target/hppa: Avoid tcg_const_i64 in trans_fid_f [PULL,43/67] target/hppa: Avoid use of tcg_const_i32 throughout [PULL,44/67] target/i386: Avoid use of tcg_const_* throughout [PULL,45/67] target/m68k: Avoid tcg_const_i32 when modified [PULL,46/67] target/m68k: Avoid tcg_const_i32 in bfop_reg [PULL,47/67] target/m68k: Avoid tcg_const_* throughout [PULL,48/67] target/mips: Split out gen_lxl [PULL,49/67] target/mips: Split out gen_lxr [PULL,50/67] target/mips: Avoid tcg_const_tl in gen_r6_ld [PULL,51/67] target/mips: Avoid tcg_const_* throughout [PULL,52/67] target/ppc: Split out gen_vx_vmul10 [PULL,53/67] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad [PULL,54/67] target/rx: Use tcg_gen_abs_i32 [PULL,55/67] target/rx: Use cpu_psw_z as temp in flags computation [PULL,56/67] target/rx: Avoid tcg_const_i32 when new temp needed [PULL,57/67] target/rx: Avoid tcg_const_i32 [PULL,58/67] target/s390x: Avoid tcg_const_i64 [PULL,59/67] target/sh4: Avoid tcg_const_i32 for TAS.B [PULL,60/67] target/sh4: Avoid tcg_const_i32 [PULL,61/67] tcg/sparc: Avoid tcg_const_tl in gen_edge [PULL,62/67] target/tricore: Split t_n as constant from temp as variable [PULL,63/67] target/tricore: Rename t_off10 and use tcg_constant_i32 [PULL,64/67] target/tricore: Use setcondi instead of explicit allocation [PULL,65/67] target/tricore: Drop some temp initialization [PULL,66/67] target/tricore: Avoid tcg_const_i32 [PULL,67/67] tcg: Replace tcg_const_i64 in tcg-op.c

Commit Message

Richard Henderson March 7, 2023, 5:58 p.m. UTC

From: Anton Johansson via <qemu-devel@nongnu.org>

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230306175230.7110-10-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/loongarch/cpu-param.h | 1 -
 1 file changed, 1 deletion(-)

diff mbox series

Patch

diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 414d8fff46..1265dc7cb5 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -13,6 +13,5 @@ 
 #define TARGET_VIRT_ADDR_SPACE_BITS 48
 
 #define TARGET_PAGE_BITS 14
-#define NB_MMU_MODES 5
 
 #endif