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[PULL,01/59] target/riscv: introduce riscv_cpu_cfg()

Message ID	20230303083740.12817-2-palmer@rivosinc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> Subject: [PULL 01/59] target/riscv: introduce riscv_cpu_cfg() Date: Fri, 3 Mar 2023 00:36:42 -0800 Message-Id: <20230303083740.12817-2-palmer@rivosinc.com> In-Reply-To: <20230303083740.12817-1-palmer@rivosinc.com> References: <20230303083740.12817-1-palmer@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Bin Meng <bmeng@tinylab.org>, LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@rivosinc.com> From: Palmer Dabbelt <palmer@rivosinc.com> To: Peter Maydell <peter.maydell@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=palmer@rivosinc.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/59] target/riscv: introduce riscv_cpu_cfg() \| expand [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() [PULL,02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa() [PULL,03/59] target/riscv: allow MISA writes as experimental [PULL,04/59] target/riscv: remove RISCV_FEATURE_DEBUG [PULL,05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP [PULL,06/59] target/riscv: remove RISCV_FEATURE_EPMP [PULL,07/59] target/riscv: remove RISCV_FEATURE_PMP [PULL,08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() [PULL,09/59] target/riscv: remove RISCV_FEATURE_MMU [PULL,10/59] target/riscv/cpu: remove CPUArchState::features and friends [PULL,11/59] target/riscv: Fix the relationship between Zfhmin and Zfh [PULL,12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx [PULL,13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin [PULL,14/59] target/riscv: Add cfg properties for Zv* extensions [PULL,15/59] target/riscv: Fix relationship between V, Zve, F and D [PULL,16/59] target/riscv: Add property check for Zvfh{min} extensions [PULL,17/59] target/riscv: Indent fixes in cpu.c [PULL,18/59] target/riscv: Simplify check for Zve32f and Zve64f [PULL,19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc [PULL,20/59] target/riscv: Remove redundunt check for zve32f and zve64f [PULL,21/59] target/riscv: Add support for Zvfh/zvfhmin extensions [PULL,22/59] target/riscv: Fix check for vector load/store instructions when EEW=64 [PULL,23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc [PULL,24/59] target/riscv: Expose properties for Zv extensions [PULL,25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR [PULL,26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() [PULL,27/59] target/riscv: Use g_assert() for the predicate() NULL check [PULL,28/59] target/riscv: gdbstub: Minor change for better readability [PULL,29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled [PULL,30/59] target/riscv: Coding style fixes in csr.c [PULL,31/59] target/riscv: Use 'bool' type for read_only [PULL,32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit [PULL,33/59] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 [PULL,35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() [PULL,36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml [PULL,37/59] target/riscv: Allow debugger to access user timer and counter CSRs [PULL,38/59] target/riscv: Allow debugger to access seed CSR [PULL,39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs [PULL,40/59] target/riscv: Allow debugger to access sstc CSRs [PULL,41/59] target/riscv: Drop priv level check in mseccfg predicate() [PULL,42/59] target/riscv: Group all predicate() routines together [PULL,43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages [PULL,44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair [PULL,45/59] target/riscv: Add support for Zicond extension [PULL,46/59] hw/riscv: Skip re-generating DT nodes for a given DTB [PULL,47/59] hw/riscv: Move the dtb load bits outside of create_fdt() [PULL,48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensio… [PULL,49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg [PULL,50/59] target/riscv: Add csr support for svadu [PULL,51/59] target/riscv: Add envcfg.PBMTE related check in address translation [PULL,52/59] target/riscv: Add envcfg.HADE related check in address translation [PULL,53/59] target/riscv: Export Svadu property [PULL,54/59] target/riscv/csr.c: use env_archcpu() in ctr() [PULL,55/59] target/riscv/csr.c: simplify mctr() [PULL,56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers [PULL,57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig [PULL,58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s() [PULL,59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig

Commit Message

Palmer Dabbelt March 3, 2023, 8:36 a.m. UTC

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230222185205.355361-2-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 target/riscv/cpu.h | 5 +++++
 1 file changed, 5 insertions(+)

diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 31537fc05f..7ee22cbfa1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -654,6 +654,11 @@  static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 #endif
 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
+static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+{
+    return &env_archcpu(env)->cfg;
+}
+
 #if defined(TARGET_RISCV32)
 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 #else