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[95.127.39.43]) by smtp.gmail.com with ESMTPSA id o14-20020a5d408e000000b002bfd524255esm497315wrp.43.2023.03.02.14.41.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 02 Mar 2023 14:41:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: John Snow , David Woodhouse , BALATON Zoltan , =?utf-8?q?Herv=C3=A9_Poussineau?= , qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v3 03/18] hw/i386/pc_piix: Wire PIIX3 IDE ouput IRQs to ISA bus IRQs 14/15 Date: Thu, 2 Mar 2023 23:40:43 +0100 Message-Id: <20230302224058.43315-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230302224058.43315-1-philmd@linaro.org> References: <20230302224058.43315-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since pc_init1() has access to the ISABus*, retrieve the ISA IRQs with isa_bus_get_irq(). Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 126b6c11df..1e90b9ff0d 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -277,7 +277,13 @@ static void pc_init1(MachineState *machine, if (pcmc->pci_enabled) { PCIDevice *dev; - dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE); + dev = pci_new_multifunction(piix3_devfn + 1, false, TYPE_PIIX3_IDE); + qdev_connect_gpio_out_named(DEVICE(dev), "ide-irq", 0, + isa_bus_get_irq(isa_bus, 14)); + qdev_connect_gpio_out_named(DEVICE(dev), "ide-irq", 1, + isa_bus_get_irq(isa_bus, 15)); + pci_realize_and_unref(dev, pci_bus, &error_fatal); + pci_ide_create_devs(dev); idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");