@@ -50,6 +50,7 @@ struct PIIXState {
#endif
uint64_t pic_levels;
+ qemu_irq cpu_intr;
qemu_irq *pic;
/* This member isn't used. Just for save/load compatibility */
@@ -42,33 +42,10 @@
#include "sysemu/runstate.h"
#include "qom/object.h"
-struct PIIX4State {
- PCIDevice dev;
- qemu_irq cpu_intr;
- qemu_irq *isa;
-
- MC146818RtcState rtc;
- PCIIDEState ide;
- UHCIState uhci;
- PIIX4PMState pm;
-
- uint32_t smb_io_base;
-
- /* Reset Control Register */
- MemoryRegion rcr_mem;
- uint8_t rcr;
-
- bool has_acpi;
- bool has_usb;
- bool smm_enabled;
-};
-
-OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
-
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
PCIBus *bus = pci_get_bus(&s->dev);
/* now we change the pic irq level according to the piix irq mappings */
@@ -82,13 +59,13 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
- qemu_set_irq(s->isa[pic_irq], pic_level);
+ qemu_set_irq(s->pic[pic_irq], pic_level);
}
}
static void piix4_isa_reset(DeviceState *dev)
{
- PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; // master, memory and I/O
@@ -123,12 +100,13 @@ static void piix4_isa_reset(DeviceState *dev)
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
+ d->pic_levels = 0; /* not used in PIIX4 */
d->rcr = 0;
}
static int piix4_post_load(void *opaque, int version_id)
{
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
if (version_id == 2) {
s->rcr = 0;
@@ -143,22 +121,22 @@ static const VMStateDescription vmstate_piix4 = {
.minimum_version_id = 2,
.post_load = piix4_post_load,
.fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX4State),
- VMSTATE_UINT8_V(rcr, PIIX4State, 3),
+ VMSTATE_PCI_DEVICE(dev, PIIXState),
+ VMSTATE_UINT8_V(rcr, PIIXState, 3),
VMSTATE_END_OF_LIST()
}
};
static void piix4_request_i8259_irq(void *opaque, int irq, int level)
{
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
}
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
if (val & 4) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@@ -170,7 +148,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
{
- PIIX4State *s = opaque;
+ PIIXState *s = opaque;
return s->rcr;
}
@@ -187,7 +165,7 @@ static const MemoryRegionOps piix4_rcr_ops = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
- PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+ PIIXState *s = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
qemu_irq *i8259_out_irq;
@@ -208,10 +186,10 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize i8259 pic */
i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
- s->isa = i8259_init(isa_bus, *i8259_out_irq);
+ s->pic = i8259_init(isa_bus, *i8259_out_irq);
/* initialize ISA irqs */
- isa_bus_register_input_irqs(isa_bus, s->isa);
+ isa_bus_register_input_irqs(isa_bus, s->pic);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
@@ -251,7 +229,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
return;
}
- qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
+ qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->pic[9]);
}
pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
@@ -259,17 +237,17 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
static void piix4_init(Object *obj)
{
- PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+ PIIXState *s = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
}
static Property piix4_props[] = {
- DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0),
- DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true),
- DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true),
- DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false),
+ DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
+ DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
+ DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
+ DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -297,7 +275,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX4State),
+ .instance_size = sizeof(PIIXState),
.instance_init = piix4_init,
.class_init = piix4_class_init,
.interfaces = (InterfaceInfo[]) {
PIIX4 has its own, private PIIX4State structure. PIIX3 has almost the same structure, provided in a public header. So reuse it and add a cpu_intr attribute which is only used by PIIX4. Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- include/hw/southbridge/piix.h | 1 + hw/isa/piix4.c | 62 +++++++++++------------------------ 2 files changed, 21 insertions(+), 42 deletions(-)