| Message ID | 20230227071046.1445572-1-gaosong@loongson.cn |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] target/loongarch: Implement Chip Configuraiton Version Register(0x0000) | expand |
On 2/26/23 21:10, Song Gao wrote: > According to the 3A5000 manual 4.1 implement Chip Configuration > Version Register(0x0000). The manual does not state that 0x0018 is > reserved for the vendor name and 0x0028 is reserved for the chip name. > > Signed-off-by: Song Gao <gaosong@loongson.cn> > --- > target/loongarch/cpu.c | 2 ++ > target/loongarch/cpu.h | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c > index 290ab4d526..d1c803c9d6 100644 > --- a/target/loongarch/cpu.c > +++ b/target/loongarch/cpu.c > @@ -545,6 +545,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr, > static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) > { > switch (addr) { > + case VERSION_REG: > + return 0x11ULL; This one is back in manual v1.03. I can't find manual 4.1? > +#define VENDOR_RESERVED_REG 0x18 > +#define CPUNAME_RESERVED_REG 0x28 Since these are unused, perhaps omit them? Either way, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
在 2023/2/28 上午3:37, Richard Henderson 写道: > On 2/26/23 21:10, Song Gao wrote: >> According to the 3A5000 manual 4.1 implement Chip Configuration >> Version Register(0x0000). The manual does not state that 0x0018 is >> reserved for the vendor name and 0x0028 is reserved for the chip name. >> >> Signed-off-by: Song Gao <gaosong@loongson.cn> >> --- >> target/loongarch/cpu.c | 2 ++ >> target/loongarch/cpu.h | 3 +++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c >> index 290ab4d526..d1c803c9d6 100644 >> --- a/target/loongarch/cpu.c >> +++ b/target/loongarch/cpu.c >> @@ -545,6 +545,8 @@ static void loongarch_qemu_write(void *opaque, >> hwaddr addr, >> static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, >> unsigned size) >> { >> switch (addr) { >> + case VERSION_REG: >> + return 0x11ULL; > > This one is back in manual v1.03. > I can't find manual 4.1? Oh, Chapter 4 Section 1. I will correct it. > >> +#define VENDOR_RESERVED_REG 0x18 >> +#define CPUNAME_RESERVED_REG 0x28 > > Since these are unused, perhaps omit them? > OK. Thanks. Song Gao > Either way, > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > > r~
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 290ab4d526..d1c803c9d6 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -545,6 +545,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr, static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) { switch (addr) { + case VERSION_REG: + return 0x11ULL; case FEATURE_REG: return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 1ULL << IOCSRF_CSRIPI; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index e35cf65597..eabb66fe2f 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -27,9 +27,12 @@ #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define VERSION_REG 0x0 #define FEATURE_REG 0x8 #define VENDOR_REG 0x10 +#define VENDOR_RESERVED_REG 0x18 #define CPUNAME_REG 0x20 +#define CPUNAME_RESERVED_REG 0x28 #define MISC_FUNC_REG 0x420 #define IOCSRM_EXTIOI_EN 48
According to the 3A5000 manual 4.1 implement Chip Configuration Version Register(0x0000). The manual does not state that 0x0018 is reserved for the vendor name and 0x0028 is reserved for the chip name. Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 3 +++ 2 files changed, 5 insertions(+)