| Message ID | 20230227054233.390271-56-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Remove tcg_const_* | expand |
On 27/02/2023 05:42, Richard Henderson wrote: > All remaining uses are strictly read-only. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/sparc/translate.c | 80 +++++++++++++++++++--------------------- > 1 file changed, 38 insertions(+), 42 deletions(-) > > diff --git a/target/sparc/translate.c b/target/sparc/translate.c > index 925023adef..137bdc5159 100644 > --- a/target/sparc/translate.c > +++ b/target/sparc/translate.c > @@ -550,7 +550,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) > if (!(env->y & 1)) > T1 = 0; > */ > - zero = tcg_const_tl(0); > + zero = tcg_constant_tl(0); > tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff); > tcg_gen_andi_tl(r_temp, cpu_y, 0x1); > tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); > @@ -928,8 +928,8 @@ static void gen_branch_n(DisasContext *dc, target_ulong pc1) > tcg_gen_mov_tl(cpu_pc, cpu_npc); > > tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); > - t = tcg_const_tl(pc1); > - z = tcg_const_tl(0); > + t = tcg_constant_tl(pc1); > + z = tcg_constant_tl(0); > tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc); > > dc->pc = DYNAMIC_PC; > @@ -938,9 +938,9 @@ static void gen_branch_n(DisasContext *dc, target_ulong pc1) > > static inline void gen_generic_branch(DisasContext *dc) > { > - TCGv npc0 = tcg_const_tl(dc->jump_pc[0]); > - TCGv npc1 = tcg_const_tl(dc->jump_pc[1]); > - TCGv zero = tcg_const_tl(0); > + TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]); > + TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]); > + TCGv zero = tcg_constant_tl(0); > > tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); > } > @@ -981,18 +981,14 @@ static inline void save_state(DisasContext *dc) > > static void gen_exception(DisasContext *dc, int which) > { > - TCGv_i32 t; > - > save_state(dc); > - t = tcg_const_i32(which); > - gen_helper_raise_exception(cpu_env, t); > + gen_helper_raise_exception(cpu_env, tcg_constant_i32(which)); > dc->base.is_jmp = DISAS_NORETURN; > } > > static void gen_check_align(TCGv addr, int mask) > { > - TCGv_i32 r_mask = tcg_const_i32(mask); > - gen_helper_check_align(cpu_env, addr, r_mask); > + gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask)); > } > > static inline void gen_mov_pc_npc(DisasContext *dc) > @@ -1074,7 +1070,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, > cmp->cond = logic_cond[cond]; > do_compare_dst_0: > cmp->is_bool = false; > - cmp->c2 = tcg_const_tl(0); > + cmp->c2 = tcg_constant_tl(0); > #ifdef TARGET_SPARC64 > if (!xcc) { > cmp->c1 = tcg_temp_new(); > @@ -1127,7 +1123,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, > cmp->cond = TCG_COND_NE; > cmp->is_bool = true; > cmp->c1 = r_dst = tcg_temp_new(); > - cmp->c2 = tcg_const_tl(0); > + cmp->c2 = tcg_constant_tl(0); > > switch (cond) { > case 0x0: > @@ -1192,7 +1188,7 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) > cmp->cond = TCG_COND_NE; > cmp->is_bool = true; > cmp->c1 = r_dst = tcg_temp_new(); > - cmp->c2 = tcg_const_tl(0); > + cmp->c2 = tcg_constant_tl(0); > > switch (cc) { > default: > @@ -1307,7 +1303,7 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) > cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]); > cmp->is_bool = false; > cmp->c1 = r_src; > - cmp->c2 = tcg_const_tl(0); > + cmp->c2 = tcg_constant_tl(0); > } > > static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) > @@ -1908,7 +1904,7 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, > > static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) > { > - TCGv m1 = tcg_const_tl(0xff); > + TCGv m1 = tcg_constant_tl(0xff); > gen_address_mask(dc, addr); > tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); > } > @@ -2163,8 +2159,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, > break; > default: > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(memop); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(memop); > > save_state(dc); > #ifdef TARGET_SPARC64 > @@ -2217,7 +2213,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, > { > TCGv saddr = tcg_temp_new(); > TCGv daddr = tcg_temp_new(); > - TCGv four = tcg_const_tl(4); > + TCGv four = tcg_constant_tl(4); > TCGv_i32 tmp = tcg_temp_new_i32(); > int i; > > @@ -2236,8 +2232,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, > #endif > default: > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(memop & MO_SIZE); > > save_state(dc); > #ifdef TARGET_SPARC64 > @@ -2313,15 +2309,15 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) > if (tb_cflags(dc->base.tb) & CF_PARALLEL) { > gen_helper_exit_atomic(cpu_env); > } else { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(MO_UB); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(MO_UB); > TCGv_i64 s64, t64; > > save_state(dc); > t64 = tcg_temp_new_i64(); > gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); > > - s64 = tcg_const_i64(0xff); > + s64 = tcg_constant_i64(0xff); > gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); > > tcg_gen_trunc_i64_tl(dst, t64); > @@ -2382,7 +2378,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, > > /* The first operation checks required alignment. */ > memop = da.memop | MO_ALIGN_64; > - eight = tcg_const_tl(8); > + eight = tcg_constant_tl(8); > for (i = 0; ; ++i) { > tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, > da.mem_idx, memop); > @@ -2409,8 +2405,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, > > default: > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(da.memop); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(da.memop); > > save_state(dc); > /* According to the table in the UA2011 manual, the only > @@ -2491,7 +2487,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, > > /* The first operation checks required alignment. */ > memop = da.memop | MO_ALIGN_64; > - eight = tcg_const_tl(8); > + eight = tcg_constant_tl(8); > for (i = 0; ; ++i) { > tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, > da.mem_idx, memop); > @@ -2566,8 +2562,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) > real hardware allows others. This can be seen with e.g. > FreeBSD 10.3 wrt ASI_IC_TAG. */ > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(da.memop); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(da.memop); > TCGv_i64 tmp = tcg_temp_new_i64(); > > save_state(dc); > @@ -2625,8 +2621,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, > /* ??? In theory we've handled all of the ASIs that are valid > for stda, and this should raise DAE_invalid_asi. */ > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(da.memop); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(da.memop); > TCGv_i64 t64 = tcg_temp_new_i64(); > > /* See above. */ > @@ -2686,8 +2682,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) > break; > default: > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(MO_UQ); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); > > save_state(dc); > gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); > @@ -2724,7 +2720,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, > as a cacheline-style operation. */ > { > TCGv d_addr = tcg_temp_new(); > - TCGv eight = tcg_const_tl(8); > + TCGv eight = tcg_constant_tl(8); > int i; > > tcg_gen_andi_tl(d_addr, addr, -8); > @@ -2736,8 +2732,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, > break; > default: > { > - TCGv_i32 r_asi = tcg_const_i32(da.asi); > - TCGv_i32 r_mop = tcg_const_i32(MO_UQ); > + TCGv_i32 r_asi = tcg_constant_i32(da.asi); > + TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); > > save_state(dc); > gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); > @@ -2786,7 +2782,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) > s1 = gen_load_fpr_F(dc, rs); > s2 = gen_load_fpr_F(dc, rd); > dst = gen_dest_fpr_F(dc); > - zero = tcg_const_i32(0); > + zero = tcg_constant_i32(0); > > tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); > > @@ -3215,7 +3211,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) > TCGv_i32 r_const; > > r_tickptr = tcg_temp_new_ptr(); > - r_const = tcg_const_i32(dc->mem_idx); > + r_const = tcg_constant_i32(dc->mem_idx); > tcg_gen_ld_ptr(r_tickptr, cpu_env, > offsetof(CPUSPARCState, tick)); > if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { > @@ -3267,7 +3263,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) > TCGv_i32 r_const; > > r_tickptr = tcg_temp_new_ptr(); > - r_const = tcg_const_i32(dc->mem_idx); > + r_const = tcg_constant_i32(dc->mem_idx); > tcg_gen_ld_ptr(r_tickptr, cpu_env, > offsetof(CPUSPARCState, stick)); > if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { > @@ -3397,7 +3393,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) > TCGv_i32 r_const; > > r_tickptr = tcg_temp_new_ptr(); > - r_const = tcg_const_i32(dc->mem_idx); > + r_const = tcg_constant_i32(dc->mem_idx); > tcg_gen_ld_ptr(r_tickptr, cpu_env, > offsetof(CPUSPARCState, tick)); > if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> ATB, Mark.
On 27/2/23 06:42, Richard Henderson wrote: > All remaining uses are strictly read-only. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/sparc/translate.c | 80 +++++++++++++++++++--------------------- > 1 file changed, 38 insertions(+), 42 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 925023adef..137bdc5159 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -550,7 +550,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) if (!(env->y & 1)) T1 = 0; */ - zero = tcg_const_tl(0); + zero = tcg_constant_tl(0); tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff); tcg_gen_andi_tl(r_temp, cpu_y, 0x1); tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); @@ -928,8 +928,8 @@ static void gen_branch_n(DisasContext *dc, target_ulong pc1) tcg_gen_mov_tl(cpu_pc, cpu_npc); tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - t = tcg_const_tl(pc1); - z = tcg_const_tl(0); + t = tcg_constant_tl(pc1); + z = tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc); dc->pc = DYNAMIC_PC; @@ -938,9 +938,9 @@ static void gen_branch_n(DisasContext *dc, target_ulong pc1) static inline void gen_generic_branch(DisasContext *dc) { - TCGv npc0 = tcg_const_tl(dc->jump_pc[0]); - TCGv npc1 = tcg_const_tl(dc->jump_pc[1]); - TCGv zero = tcg_const_tl(0); + TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]); + TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]); + TCGv zero = tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); } @@ -981,18 +981,14 @@ static inline void save_state(DisasContext *dc) static void gen_exception(DisasContext *dc, int which) { - TCGv_i32 t; - save_state(dc); - t = tcg_const_i32(which); - gen_helper_raise_exception(cpu_env, t); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(which)); dc->base.is_jmp = DISAS_NORETURN; } static void gen_check_align(TCGv addr, int mask) { - TCGv_i32 r_mask = tcg_const_i32(mask); - gen_helper_check_align(cpu_env, addr, r_mask); + gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask)); } static inline void gen_mov_pc_npc(DisasContext *dc) @@ -1074,7 +1070,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, cmp->cond = logic_cond[cond]; do_compare_dst_0: cmp->is_bool = false; - cmp->c2 = tcg_const_tl(0); + cmp->c2 = tcg_constant_tl(0); #ifdef TARGET_SPARC64 if (!xcc) { cmp->c1 = tcg_temp_new(); @@ -1127,7 +1123,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, cmp->cond = TCG_COND_NE; cmp->is_bool = true; cmp->c1 = r_dst = tcg_temp_new(); - cmp->c2 = tcg_const_tl(0); + cmp->c2 = tcg_constant_tl(0); switch (cond) { case 0x0: @@ -1192,7 +1188,7 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) cmp->cond = TCG_COND_NE; cmp->is_bool = true; cmp->c1 = r_dst = tcg_temp_new(); - cmp->c2 = tcg_const_tl(0); + cmp->c2 = tcg_constant_tl(0); switch (cc) { default: @@ -1307,7 +1303,7 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]); cmp->is_bool = false; cmp->c1 = r_src; - cmp->c2 = tcg_const_tl(0); + cmp->c2 = tcg_constant_tl(0); } static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) @@ -1908,7 +1904,7 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) { - TCGv m1 = tcg_const_tl(0xff); + TCGv m1 = tcg_constant_tl(0xff); gen_address_mask(dc, addr); tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); } @@ -2163,8 +2159,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, break; default: { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(memop); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(memop); save_state(dc); #ifdef TARGET_SPARC64 @@ -2217,7 +2213,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, { TCGv saddr = tcg_temp_new(); TCGv daddr = tcg_temp_new(); - TCGv four = tcg_const_tl(4); + TCGv four = tcg_constant_tl(4); TCGv_i32 tmp = tcg_temp_new_i32(); int i; @@ -2236,8 +2232,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, #endif default: { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(memop & MO_SIZE); save_state(dc); #ifdef TARGET_SPARC64 @@ -2313,15 +2309,15 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) if (tb_cflags(dc->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(MO_UB); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(MO_UB); TCGv_i64 s64, t64; save_state(dc); t64 = tcg_temp_new_i64(); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); - s64 = tcg_const_i64(0xff); + s64 = tcg_constant_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); tcg_gen_trunc_i64_tl(dst, t64); @@ -2382,7 +2378,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, /* The first operation checks required alignment. */ memop = da.memop | MO_ALIGN_64; - eight = tcg_const_tl(8); + eight = tcg_constant_tl(8); for (i = 0; ; ++i) { tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da.mem_idx, memop); @@ -2409,8 +2405,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, default: { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(da.memop); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(da.memop); save_state(dc); /* According to the table in the UA2011 manual, the only @@ -2491,7 +2487,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, /* The first operation checks required alignment. */ memop = da.memop | MO_ALIGN_64; - eight = tcg_const_tl(8); + eight = tcg_constant_tl(8); for (i = 0; ; ++i) { tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da.mem_idx, memop); @@ -2566,8 +2562,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) real hardware allows others. This can be seen with e.g. FreeBSD 10.3 wrt ASI_IC_TAG. */ { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(da.memop); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(da.memop); TCGv_i64 tmp = tcg_temp_new_i64(); save_state(dc); @@ -2625,8 +2621,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(da.memop); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(da.memop); TCGv_i64 t64 = tcg_temp_new_i64(); /* See above. */ @@ -2686,8 +2682,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) break; default: { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(MO_UQ); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); save_state(dc); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); @@ -2724,7 +2720,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, as a cacheline-style operation. */ { TCGv d_addr = tcg_temp_new(); - TCGv eight = tcg_const_tl(8); + TCGv eight = tcg_constant_tl(8); int i; tcg_gen_andi_tl(d_addr, addr, -8); @@ -2736,8 +2732,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, break; default: { - TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_mop = tcg_const_i32(MO_UQ); + TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); save_state(dc); gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); @@ -2786,7 +2782,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) s1 = gen_load_fpr_F(dc, rs); s2 = gen_load_fpr_F(dc, rd); dst = gen_dest_fpr_F(dc); - zero = tcg_const_i32(0); + zero = tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); @@ -3215,7 +3211,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) TCGv_i32 r_const; r_tickptr = tcg_temp_new_ptr(); - r_const = tcg_const_i32(dc->mem_idx); + r_const = tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { @@ -3267,7 +3263,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) TCGv_i32 r_const; r_tickptr = tcg_temp_new_ptr(); - r_const = tcg_const_i32(dc->mem_idx); + r_const = tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { @@ -3397,7 +3393,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) TCGv_i32 r_const; r_tickptr = tcg_temp_new_ptr(); - r_const = tcg_const_i32(dc->mem_idx); + r_const = tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
All remaining uses are strictly read-only. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/translate.c | 80 +++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 42 deletions(-)