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Fri, 24 Feb 2023 00:37:23 -0800 (PST) From: Sunil V L To: Palmer Dabbelt , Alistair Francis , Bin Meng Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Andrew Jones , Anup Patel , Atish Kumar Patra , Daniel Henrique Barboza , Sunil V L Subject: [PATCH V4 5/8] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT Date: Fri, 24 Feb 2023 14:06:58 +0530 Message-Id: <20230224083701.2657063-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230224083701.2657063-1-sunilvl@ventanamicro.com> References: <20230224083701.2657063-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=sunilvl@ventanamicro.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add Multiple APIC Description Table (MADT) with the RINTC structure for each cpu. Signed-off-by: Sunil V L Acked-by: Alistair Francis Reviewed-by: Andrew Jones --- hw/riscv/virt-acpi-build.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 3a5e2e6d53..8b85b34c55 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -32,6 +32,7 @@ #include "sysemu/reset.h" #include "migration/vmstate.h" #include "hw/riscv/virt.h" +#include "hw/riscv/numa.h" #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -132,6 +133,46 @@ static void build_dsdt(GArray *table_data, free_aml_allocator(); } +/* MADT */ +static void build_madt(GArray *table_data, + BIOSLinker *linker, + RISCVVirtState *s) +{ + MachineState *ms = MACHINE(s); + int socket; + uint16_t base_hartid = 0; + uint32_t cpu_id = 0; + + AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, + .oem_table_id = s->oem_table_id }; + + acpi_table_begin(&table, table_data); + /* Local Interrupt Controller Address */ + build_append_int_noprefix(table_data, 0, 4); + build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */ + + /* RISC-V Local INTC structures per HART */ + for (socket = 0; socket < riscv_socket_count(ms); socket++) { + base_hartid = riscv_socket_first_hartid(ms, socket); + + for (int i = 0; i < s->soc[socket].num_harts; i++) { + build_append_int_noprefix(table_data, 0x18, 1); /* Type */ + build_append_int_noprefix(table_data, 20, 1); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Version */ + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ + build_append_int_noprefix(table_data, 1, 4); /* Flags */ + build_append_int_noprefix(table_data, + (base_hartid + i), 8); /* Hart ID */ + + /* ACPI Processor UID */ + build_append_int_noprefix(table_data, cpu_id, 4); + cpu_id++; + } + } + + acpi_table_end(linker, &table); +} + static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) { GArray *table_offsets; @@ -153,6 +194,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_fadt_rev6(tables_blob, tables->linker, s, dsdt); + acpi_add_table(table_offsets, tables_blob); + build_madt(tables_blob, tables->linker, s); + /* XSDT is pointed to by RSDP */ xsdt = tables_blob->len; build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,