Message ID | 20230217203445.51077-5-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: Add support for Zicbo[m,z,p] instructions | expand |
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3788f86528..1aebd37572 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -134,6 +134,7 @@ addi ............ ..... 000 ..... 0010011 @i slti ............ ..... 010 ..... 0010011 @i sltiu ............ ..... 011 ..... 0010011 @i xori ............ ..... 100 ..... 0010011 @i +# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded. ori ............ ..... 110 ..... 0010011 @i andi ............ ..... 111 ..... 0010011 @i slli 00000. ...... ..... 001 ..... 0010011 @sh