| Message ID | 20230216215550.1011637-4-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | make write_misa a no-op and FEATURE_* cleanups | expand |
On 2023/2/17 5:55, Daniel Henrique Barboza wrote: > RISCV_FEATURE_DEBUG will always follow the value defined by > cpu->cfg.debug flag. Read the flag instead. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> > Reviewed-by: Bin Meng <bmeng@tinylab.org> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > --- > target/riscv/cpu.c | 6 +----- > target/riscv/cpu.h | 1 - > target/riscv/cpu_helper.c | 2 +- > target/riscv/csr.c | 2 +- > target/riscv/machine.c | 3 +-- > 5 files changed, 4 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 93b52b826c..e34a5e3f11 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj) > set_default_nan_mode(1, &env->fp_status); > > #ifndef CONFIG_USER_ONLY > - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { > + if (cpu->cfg.debug) { > riscv_trigger_init(env); > } > > @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > - if (cpu->cfg.debug) { > - riscv_set_feature(env, RISCV_FEATURE_DEBUG); > - } > - > > #ifndef CONFIG_USER_ONLY > if (cpu->cfg.ext_sstc) { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5e9626837b..2afb705930 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -89,7 +89,6 @@ enum { > RISCV_FEATURE_MMU, > RISCV_FEATURE_PMP, > RISCV_FEATURE_EPMP, > - RISCV_FEATURE_DEBUG > }; > > /* Privileged specification version */ > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index ad8d82662c..4cdd247c6c 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, > get_field(env->mstatus_hs, MSTATUS_VS)); > } > - if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { > + if (cpu->cfg.debug && !icount_enabled()) { > flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); > } > #endif > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index f7862ff4a4..58af2c0e66 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno) > > static RISCVException debug(CPURISCVState *env, int csrno) > { > - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { > + if (riscv_cpu_cfg(env)->debug) { > return RISCV_EXCP_NONE; > } > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index c6ce318cce..4634968898 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = { > static bool debug_needed(void *opaque) > { > RISCVCPU *cpu = opaque; > - CPURISCVState *env = &cpu->env; > > - return riscv_feature(env, RISCV_FEATURE_DEBUG); > + return cpu->cfg.debug; > } > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > static int debug_post_load(void *opaque, int version_id)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93b52b826c..e34a5e3f11 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (cpu->cfg.debug) { riscv_trigger_init(env); } @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.debug) { - riscv_set_feature(env, RISCV_FEATURE_DEBUG); - } - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5e9626837b..2afb705930 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_DEBUG }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ad8d82662c..4cdd247c6c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } - if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f7862ff4a4..58af2c0e66 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (riscv_cpu_cfg(env)->debug) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ce318cce..4634968898 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = { static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_DEBUG); + return cpu->cfg.debug; } static int debug_post_load(void *opaque, int version_id)