| Message ID | 20230214192356.319991-3-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | enable write_misa() and RISCV_FEATURE_* cleanups | expand |
On Wed, Feb 15, 2023 at 3:26 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > We're going to do changes that requires accessing the RISCVCPUConfig > struct from the RISCVCPU, having access only to a CPURISCVState 'env' > pointer. Add a helper to make the code easier to read. > > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.h | 5 +++++ > 1 file changed, 5 insertions(+) > Reviewed-by: Bin Meng <bmeng@tinylab.org>
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7128438d8e..5e4d056772 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) +static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env) +{ + return env_archcpu(env)->cfg; +} + #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else