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[92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:16 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 06/12] hw/pci-host/q35: Initialize properties just once Date: Tue, 14 Feb 2023 14:14:35 +0100 Message-Id: <20230214131441.101760-7-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Although not used there, the attributes for Q35's "pci-hole64-size" and "short_root_bus" properties currently reside in its child device. This causes the default values to be overwritten during the child's object_initialize() phase. Avoid this by moving both attributes into the host device. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/q35.h | 5 +++-- hw/pci-host/q35.c | 20 +++++--------------- 2 files changed, 8 insertions(+), 17 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index fcbe57b42d..93e41ffbee 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -54,8 +54,6 @@ struct MCHPCIState { Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; - uint64_t pci_hole64_size; - uint32_t short_root_bus; uint16_t ext_tseg_mbytes; }; @@ -64,7 +62,10 @@ struct Q35PCIHost { PCIExpressHost parent_obj; /*< public >*/ + uint64_t pci_hole64_size; + uint32_t short_root_bus; bool pci_hole64_fix; + MCHPCIState mch; }; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0e198f97a7..03aa08dae5 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -76,7 +76,7 @@ static const char *q35_host_root_bus_path(PCIHostState *host_bridge, Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); /* For backwards compat with old device paths */ - if (s->mch.short_root_bus) { + if (s->short_root_bus) { return "0000"; } return "0000:00"; @@ -161,27 +161,19 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, pci_bus_get_w64_range(h->bus, &w64); value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; - hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); + hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); if (s->pci_hole64_fix && value < hole64_end) { value = hole64_end; } visit_type_uint64(v, name, &value, errp); } -/* - * NOTE: setting defaults for the mch.* fields in this table - * doesn't work, because mch is a separate QOM object that is - * zeroed by the object_initialize(&s->mch, ...) call inside - * q35_host_initfn(). The default values for those - * properties need to be initialized manually by - * q35_host_initfn() after the object_initialize() call. - */ static Property q35_host_props[] = { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, - mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), - DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), + pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), + DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, short_root_bus, 0), DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, mch.below_4g_mem_size, 0), DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, @@ -218,9 +210,7 @@ static void q35_host_initfn(Object *obj) object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE); qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); - /* mch's object_initialize resets the default value, set it again */ - qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, - Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", q35_host_get_pci_hole_start, NULL, NULL, NULL);