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[92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:24 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 12/12] hw/pci-host/q35: Move MemoryRegion pointers to host device Date: Tue, 14 Feb 2023 14:14:41 +0100 Message-Id: <20230214131441.101760-13-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The pointers are set through the host device's properties and are only used during its realization phase. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/q35.h | 10 +++---- hw/pci-host/q35.c | 56 +++++++++++++++++++-------------------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index a04d5f1a17..9b9ce48ca8 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -40,11 +40,6 @@ struct MCHPCIState { PCIDevice parent_obj; /*< public >*/ - MemoryRegion *ram_memory; - MemoryRegion *pci_address_space; - MemoryRegion *system_memory; - MemoryRegion *address_space_io; - MemoryRegion *smram; PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT]; MemoryRegion smram_region, open_high_smram; MemoryRegion low_smram, high_smram; @@ -61,6 +56,11 @@ struct Q35PCIHost { PCIExpressHost parent_obj; /*< public >*/ + MemoryRegion *ram_memory; + MemoryRegion *pci_address_space; + MemoryRegion *system_memory; + MemoryRegion *address_space_io; + MemoryRegion *smram; Range pci_hole; uint64_t pci_hole64_size; uint32_t short_root_bus; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 3a7f9185a3..cb8ea58c25 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -79,11 +79,11 @@ static void q35_host_realize(DeviceState *dev, Error **errp) return; } - memory_region_add_subregion(s->mch.address_space_io, + memory_region_add_subregion(s->address_space_io, MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); - memory_region_add_subregion(s->mch.address_space_io, + memory_region_add_subregion(s->address_space_io, MCH_HOST_BRIDGE_CONFIG_DATA, &phb->data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); @@ -99,47 +99,47 @@ static void q35_host_realize(DeviceState *dev, Error **errp) IO_APIC_DEFAULT_ADDRESS - 1); /* setup pci memory mapping */ - pc_pci_as_mapping_init(s->mch.system_memory, s->mch.pci_address_space); + pc_pci_as_mapping_init(s->system_memory, s->pci_address_space); /* if *disabled* show SMRAM to all CPUs */ memory_region_init_alias(&s->mch.smram_region, OBJECT(s), "smram-region", - s->mch.pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(s->mch.system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + memory_region_add_subregion_overlap(s->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, &s->mch.smram_region, 1); memory_region_set_enabled(&s->mch.smram_region, true); memory_region_init_alias(&s->mch.open_high_smram, OBJECT(s), "smram-open-high", - s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(s->mch.system_memory, 0xfeda0000, + memory_region_add_subregion_overlap(s->system_memory, 0xfeda0000, &s->mch.open_high_smram, 1); memory_region_set_enabled(&s->mch.open_high_smram, false); /* smram, as seen by SMM CPUs */ memory_region_init_alias(&s->mch.low_smram, OBJECT(s), "smram-low", - s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); memory_region_set_enabled(&s->mch.low_smram, true); - memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, + memory_region_add_subregion(s->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, &s->mch.low_smram); memory_region_init_alias(&s->mch.high_smram, OBJECT(s), "smram-high", - s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); memory_region_set_enabled(&s->mch.high_smram, true); - memory_region_add_subregion(s->mch.smram, 0xfeda0000, &s->mch.high_smram); + memory_region_add_subregion(s->smram, 0xfeda0000, &s->mch.high_smram); memory_region_init_io(&s->mch.tseg_blackhole, OBJECT(s), &blackhole_ops, NULL, "tseg-blackhole", 0); memory_region_set_enabled(&s->mch.tseg_blackhole, false); - memory_region_add_subregion_overlap(s->mch.system_memory, + memory_region_add_subregion_overlap(s->system_memory, s->mch.below_4g_mem_size, &s->mch.tseg_blackhole, 1); memory_region_init_alias(&s->mch.tseg_window, OBJECT(s), "tseg-window", - s->mch.ram_memory, s->mch.below_4g_mem_size, 0); + s->ram_memory, s->mch.below_4g_mem_size, 0); memory_region_set_enabled(&s->mch.tseg_window, false); - memory_region_add_subregion(s->mch.smram, s->mch.below_4g_mem_size, + memory_region_add_subregion(s->smram, s->mch.below_4g_mem_size, &s->mch.tseg_window); /* @@ -150,30 +150,30 @@ static void q35_host_realize(DeviceState *dev, Error **errp) NULL, "smbase-blackhole", MCH_HOST_BRIDGE_SMBASE_SIZE); memory_region_set_enabled(&s->mch.smbase_blackhole, false); - memory_region_add_subregion_overlap(s->mch.system_memory, + memory_region_add_subregion_overlap(s->system_memory, MCH_HOST_BRIDGE_SMBASE_ADDR, &s->mch.smbase_blackhole, 1); memory_region_init_alias(&s->mch.smbase_window, OBJECT(s), - "smbase-window", s->mch.ram_memory, + "smbase-window", s->ram_memory, MCH_HOST_BRIDGE_SMBASE_ADDR, MCH_HOST_BRIDGE_SMBASE_SIZE); memory_region_set_enabled(&s->mch.smbase_window, false); - memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMBASE_ADDR, + memory_region_add_subregion(s->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, &s->mch.smbase_window); - init_pam(&s->mch.pam_regions[0], OBJECT(s), s->mch.ram_memory, - s->mch.system_memory, s->mch.pci_address_space, + init_pam(&s->mch.pam_regions[0], OBJECT(s), s->ram_memory, + s->system_memory, s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < ARRAY_SIZE(s->mch.pam_regions) - 1; ++i) { - init_pam(&s->mch.pam_regions[i + 1], OBJECT(s), s->mch.ram_memory, - s->mch.system_memory, s->mch.pci_address_space, + init_pam(&s->mch.pam_regions[i + 1], OBJECT(s), s->ram_memory, + s->system_memory, s->pci_address_space, PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } phb->bus = pci_root_bus_new(DEVICE(s), "pcie.0", - s->mch.pci_address_space, - s->mch.address_space_io, + s->pci_address_space, + s->address_space_io, 0, TYPE_PCIE_BUS); qdev_realize(DEVICE(&s->mch), BUS(phb->bus), errp); @@ -338,23 +338,23 @@ static void q35_host_initfn(Object *obj) &pehb->size, OBJ_PROP_FLAG_READ); object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.ram_memory, + (Object **) &s->ram_memory, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_SMRAM_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.smram, + (Object **) &s->smram, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.pci_address_space, + (Object **) &s->pci_address_space, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.system_memory, + (Object **) &s->system_memory, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.address_space_io, + (Object **) &s->address_space_io, qdev_prop_allow_set_link_before_realize, 0); }