@@ -371,7 +371,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
bool dry_run)
{
MachineState *machine = MACHINE(pms);
- unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int smp_cpus = machine_topo_get_cpus(machine);
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
CPUPPCState *env = first_cpu->env_ptr;
int ret = -1;
@@ -808,7 +808,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
SysBusDevice *s;
int i, j, k;
MachineState *machine = MACHINE(pms);
- unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int smp_cpus = machine_topo_get_cpus(machine);
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
dev = qdev_new(TYPE_OPENPIC);
@@ -915,7 +915,7 @@ void ppce500_init(MachineState *machine)
struct boot_info *boot_info = NULL;
int dt_size;
int i;
- unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int smp_cpus = machine_topo_get_cpus(machine);
/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
* 4 respectively */
unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
@@ -136,7 +136,7 @@ static void ppc_core99_init(MachineState *machine)
CPUPPCState *env = NULL;
char *filename;
IrqLines *openpic_irqs;
- int i, j, k, ppc_boot_device, machine_arch, bios_size = -1;
+ int i, j, k, cpus, ppc_boot_device, machine_arch, bios_size = -1;
const char *bios_name = machine->firmware ?: PROM_FILENAME;
MemoryRegion *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0;
@@ -155,8 +155,9 @@ static void ppc_core99_init(MachineState *machine)
hwaddr nvram_addr = 0xFFF04000;
uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
+ cpus = machine_topo_get_cpus(machine);
/* init CPUs */
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
@@ -253,9 +254,9 @@ static void ppc_core99_init(MachineState *machine)
}
}
- openpic_irqs = g_new0(IrqLines, machine->smp.cpus);
+ openpic_irqs = g_new0(IrqLines, cpus);
dev = DEVICE(cpu);
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < cpus; i++) {
/* Mac99 IRQ connection between OpenPIC outputs pins
* and PowerPC input pins
*/
@@ -393,7 +394,7 @@ static void ppc_core99_init(MachineState *machine)
/* OpenPIC */
s = SYS_BUS_DEVICE(pic_dev);
k = 0;
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
}
@@ -472,8 +473,9 @@ static void ppc_core99_init(MachineState *machine)
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS,
+ (uint16_t)machine_topo_get_max_cpus(machine));
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
@@ -90,7 +90,7 @@ static void ppc_heathrow_init(MachineState *machine)
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
- int i, bios_size = -1;
+ int i, cpus, bios_size = -1;
MemoryRegion *bios = g_new(MemoryRegion, 1);
uint64_t bios_addr;
uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0;
@@ -106,8 +106,9 @@ static void ppc_heathrow_init(MachineState *machine)
void *fw_cfg;
uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
+ cpus = machine_topo_get_cpus(machine);
/* init CPUs */
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
@@ -260,7 +261,7 @@ static void ppc_heathrow_init(MachineState *machine)
}
/* Connect the heathrow PIC outputs to the 6xx bus */
- for (i = 0; i < machine->smp.cpus; i++) {
+ for (i = 0; i < cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
/* XXX: we register only 1 output pin for heathrow PIC */
@@ -315,8 +316,9 @@ static void ppc_heathrow_init(MachineState *machine)
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS,
+ (uint16_t)machine_topo_get_max_cpus(machine));
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
@@ -938,8 +938,9 @@ static void pnv_init(MachineState *machine)
exit(1);
}
- pnv->num_chips =
- machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
+ pnv->num_chips = machine_topo_get_max_cpus(machine) /
+ (machine_topo_get_smp_cores(machine) *
+ machine_topo_get_smp_threads(machine));
/*
* TODO: should we decide on how many chips we can create based
* on #cores and Venice vs. Murano vs. Naples chip type etc...,
@@ -969,9 +970,11 @@ static void pnv_init(MachineState *machine)
snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
object_property_add_child(OBJECT(pnv), chip_name, chip);
object_property_set_int(chip, "chip-id", i, &error_fatal);
- object_property_set_int(chip, "nr-cores", machine->smp.cores,
+ object_property_set_int(chip, "nr-cores",
+ machine_topo_get_smp_cores(machine),
&error_fatal);
- object_property_set_int(chip, "nr-threads", machine->smp.threads,
+ object_property_set_int(chip, "nr-threads",
+ machine_topo_get_smp_threads(machine),
&error_fatal);
/*
* The POWER8 machine use the XICS interrupt interface.
@@ -382,7 +382,8 @@ static void ibm_40p_init(MachineState *machine)
boot_device = machine->boot_config.order[0];
}
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS,
+ (uint16_t)machine_topo_get_max_cpus(machine));
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
@@ -119,7 +119,7 @@
static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
{
MachineState *ms = MACHINE(spapr);
- unsigned int smp_threads = ms->smp.threads;
+ unsigned int smp_threads = machine_topo_get_smp_threads(ms);
assert(spapr->vsmt);
return
@@ -171,7 +171,8 @@ int spapr_max_server_number(SpaprMachineState *spapr)
MachineState *ms = MACHINE(spapr);
assert(spapr->vsmt);
- return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
+ return DIV_ROUND_UP(machine_topo_get_max_cpus(ms) * spapr->vsmt,
+ machine_topo_get_smp_threads(ms));
}
static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
@@ -659,8 +660,8 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
- unsigned int smp_threads = ms->smp.threads;
- uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
+ unsigned int smp_threads = machine_topo_get_smp_threads(ms);
+ uint32_t vcpus_per_socket = smp_threads * machine_topo_get_smp_cores(ms);
uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
SpaprDrc *drc;
@@ -866,7 +867,8 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
cpu_to_be32(max_device_addr & 0xffffffff),
cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32),
cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff),
- cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
+ cpu_to_be32(machine_topo_get_max_cpus(ms) /
+ machine_topo_get_smp_threads(ms)),
};
_FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
@@ -936,7 +938,7 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
*/
_FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE +
RTAS_ERROR_LOG_MAX +
- ms->smp.max_cpus * sizeof(uint64_t) * 2 +
+ machine_topo_get_max_cpus(ms) * sizeof(uint64_t) * 2 +
sizeof(uint64_t)));
_FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
RTAS_ERROR_LOG_MAX));
@@ -2503,7 +2505,7 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
/* find cpu slot in machine->possible_cpus by core_id */
static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
{
- int index = id / ms->smp.threads;
+ int index = id / machine_topo_get_smp_threads(ms);
if (index >= ms->possible_cpus->len) {
return NULL;
@@ -2522,7 +2524,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
bool vsmt_user = !!spapr->vsmt;
int kvm_smt = kvmppc_smt_threads();
int ret;
- unsigned int smp_threads = ms->smp.threads;
+ unsigned int smp_threads = machine_topo_get_smp_threads(ms);
if (!kvm_enabled() && (smp_threads > 1)) {
error_setg(errp, "TCG cannot support more than 1 thread/core "
@@ -2594,9 +2596,9 @@ static void spapr_init_cpus(SpaprMachineState *spapr)
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
const char *type = spapr_get_cpu_core_type(machine->cpu_type);
const CPUArchIdList *possible_cpus;
- unsigned int smp_cpus = machine->smp.cpus;
- unsigned int smp_threads = machine->smp.threads;
- unsigned int max_cpus = machine->smp.max_cpus;
+ unsigned int smp_cpus = machine_topo_get_cpus(machine);
+ unsigned int smp_threads = machine_topo_get_smp_threads(machine);
+ unsigned int max_cpus = machine_topo_get_max_cpus(machine);
int boot_cores_nr = smp_cpus / smp_threads;
int i;
@@ -4002,7 +4004,7 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
const char *type = object_get_typename(OBJECT(dev));
CPUArchId *core_slot;
int index;
- unsigned int smp_threads = machine->smp.threads;
+ unsigned int smp_threads = machine_topo_get_smp_threads(machine);
if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
error_setg(errp, "CPU hotplug not supported for this machine");
@@ -4320,16 +4322,16 @@ spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
{
- return idx / ms->smp.cores % ms->numa_state->num_nodes;
+ return idx / machine_topo_get_smp_cores(ms) % ms->numa_state->num_nodes;
}
static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
{
int i;
- unsigned int smp_threads = machine->smp.threads;
- unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int smp_threads = machine_topo_get_smp_threads(machine);
+ unsigned int smp_cpus = machine_topo_get_cpus(machine);
const char *core_type;
- int spapr_max_cores = machine->smp.max_cpus / smp_threads;
+ int spapr_max_cores = machine_topo_get_max_cpus(machine) / smp_threads;
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (!mc->has_hotpluggable_cpus) {
@@ -4500,7 +4502,8 @@ bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
error_append_hint(errp, "Adjust the number of cpus to %d "
"or try to raise the number of threads per core\n",
- vcpu_id * ms->smp.threads / spapr->vsmt);
+ vcpu_id * machine_topo_get_smp_threads(ms) /
+ spapr->vsmt);
return false;
}
@@ -279,14 +279,15 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
- g_autofree char *param_val = g_strdup_printf("MaxEntCap=%d,"
- "DesMem=%" PRIu64 ","
- "DesProcs=%d,"
- "MaxPlatProcs=%d",
- ms->smp.max_cpus,
- ms->ram_size / MiB,
- ms->smp.cpus,
- ms->smp.max_cpus);
+ g_autofree char *param_val =
+ g_strdup_printf("MaxEntCap=%d,"
+ "DesMem=%" PRIu64 ","
+ "DesProcs=%d,"
+ "MaxPlatProcs=%d",
+ machine_topo_get_max_cpus(ms),
+ ms->ram_size / MiB,
+ machine_topo_get_cpus(ms),
+ machine_topo_get_max_cpus(ms));
if (pcc->n_host_threads > 0) {
/*
* Add HostThrs property. This property is not present in PAPR but