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Wed, 08 Feb 2023 22:30:27 -0800 (PST) Received: from debug.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id u15-20020aa7848f000000b00593c434b1b8sm543649pfn.48.2023.02.08.22.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Feb 2023 22:30:26 -0800 (PST) From: Deepak Gupta To: qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: Deepak Gupta , Kip Walker , qemu-riscv@nongnu.org Subject: [PATCH v1 RFC Zisslpcfi 4/9] target/riscv: helper functions for forward and backward cfi Date: Wed, 8 Feb 2023 22:29:42 -0800 Message-Id: <20230209062947.3585481-5-debug@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209062947.3585481-1-debug@rivosinc.com> References: <20230209062947.3585481-1-debug@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=debug@rivosinc.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implementation for forward cfi and backward cfi needs helper function to determine if currently fcfi and bcfi are enabled. Enable depends on privilege mode and settings in sstatus/menvcfg/henvcfg/mseccfg CSRs. Signed-off-by: Deepak Gupta Signed-off-by: Kip Walker --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 51 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 18db61a06a..d14ea4f91d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -568,6 +568,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +bool cpu_get_fcfien(CPURISCVState *env); +bool cpu_get_bcfien(CPURISCVState *env); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a28816521..a397023840 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -30,6 +30,7 @@ #include "sysemu/cpu-timers.h" #include "cpu_bits.h" #include "debug.h" +#include "pmp.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -40,6 +41,56 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } +bool cpu_get_fcfien(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* no cfi extension, return false */ + if (!env_archcpu(env)->cfg.ext_cfi) { + return false; + } + + switch (env->priv) { + case PRV_U: + return (env->mstatus & MSTATUS_UFCFIEN) ? true : false; + case PRV_S: + return (env->menvcfg & MENVCFG_SFCFIEN) ? true : false; + case PRV_M: + return (env->mseccfg & MSECCFG_MFCFIEN) ? true : false; + default: + g_assert_not_reached(); + } +#endif +} + +bool cpu_get_bcfien(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* no cfi extension, return false */ + if (!env_archcpu(env)->cfg.ext_cfi) { + return false; + } + + switch (env->priv) { + case PRV_U: + return (env->mstatus & MSTATUS_UBCFIEN) ? true : false; + + /* + * no gating for back cfi in M/S mode. back cfi is always on for + * M/S mode + */ + case PRV_S: + case PRV_M: + return true; + default: + g_assert_not_reached(); + } +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) {