diff mbox series

MAINTAINERS: Add some RISC-V reviewers

Message ID	20230209003308.738237-1-alistair.francis@opensource.wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: xmIkbIh8Q7RgobzYNWgW5px3SAILYJjBZjjeQQSbMut4FQJ0wx4/q8c/JsOtJw340lognXtlHh 9hnPzYvYatkolAnOpABJlAXo16Hm9OC9qxrIQf2JUHM9tXAC1cCWPoDR2lQc2Rjg9Rmy4RkxCW aTAEkYPtgF7G2py1C8KVX9dZFTd2u/xMvXiQMgg0ytjwI8T+lBJeNIxyj3jrUBlbPkZ8OSAS3v i98y9ut09MjMT+R3RYcxW1M2hvZgFS6NAm2Y0Oz9TW6OwezZyV9N6DxXvOqjaZ+Udz9hddwrom zew= IronPort-SDR: c0yxcdcA3sFJfV5gPBG+QLekyL7d+dkZlPi2zgUhk5JjOI4nNp4LUHjsB8mngoP1TTjf0QKQY7 3RZuwn0rvQcaHn180VvyUcM05v08lEQroD5nE/j1y4ZQys6fMFDmnWkkgCvdhzXWdXdUaAZSAR ImFzCFRf0V/haYRPSBNtE2uVdpkPY2yGjswa5uaYXis8ph+uFvWPkncYZuEjpN9Q3YpFG+j3vG 2DktEvb7VqKfAsVjxQUutsDd6fYAT6eJTKrf9BgqMNPGprdWDLQrVN08ie0lzWrGehY04cxQpp upY= WDCIronportException: Internal From: Alistair Francis <alistair.francis@opensource.wdc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: bmeng.cn@gmail.com, alistair23@gmail.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com, palmer@dabbelt.com, zhiwei_liu@linux.alibaba.com, liweiwei@iscas.ac.cn Subject: [PATCH] MAINTAINERS: Add some RISC-V reviewers Date: Thu, 9 Feb 2023 10:33:08 +1000 Message-Id: <20230209003308.738237-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=39791fc40=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	MAINTAINERS: Add some RISC-V reviewers \| expand MAINTAINERS: Add some RISC-V reviewers

Commit Message

Alistair Francis Feb. 9, 2023, 12:33 a.m. UTC

From: Alistair Francis <alistair.francis@wdc.com>

This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

Comments

LIU Zhiwei Feb. 9, 2023, 1:24 a.m. UTC | #1

On 2023/2/9 8:33, Alistair Francis wrote:

> From: Alistair Francis <alistair.francis@wdc.com>
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   MAINTAINERS | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 96e25f62ac..847bc7f131 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -287,6 +287,9 @@ RISC-V TCG CPUs
>   M: Palmer Dabbelt <palmer@dabbelt.com>
>   M: Alistair Francis <alistair.francis@wdc.com>
>   M: Bin Meng <bin.meng@windriver.com>
> +R: Weiwei Li <liweiwei@iscas.ac.cn>
> +R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> +R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

>   L: qemu-riscv@nongnu.org
>   S: Supported
>   F: target/riscv/

Weiwei Li Feb. 9, 2023, 4:35 a.m. UTC | #2

On 2023/2/9 08:33, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   MAINTAINERS | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 96e25f62ac..847bc7f131 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -287,6 +287,9 @@ RISC-V TCG CPUs
>   M: Palmer Dabbelt <palmer@dabbelt.com>
>   M: Alistair Francis <alistair.francis@wdc.com>
>   M: Bin Meng <bin.meng@windriver.com>
> +R: Weiwei Li <liweiwei@iscas.ac.cn>
> +R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> +R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>   L: qemu-riscv@nongnu.org
>   S: Supported
>   F: target/riscv/

Acked-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

Philippe Mathieu-Daudé Feb. 9, 2023, 7:06 a.m. UTC | #3

On 9/2/23 01:33, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   MAINTAINERS | 3 +++
>   1 file changed, 3 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Bin Meng Feb. 9, 2023, 9:17 a.m. UTC | #4

On Thu, Feb 9, 2023 at 8:33 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  MAINTAINERS | 3 +++
>  1 file changed, 3 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Daniel Henrique Barboza Feb. 9, 2023, 9:34 a.m. UTC | #5

On 2/8/23 21:33, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   MAINTAINERS | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 96e25f62ac..847bc7f131 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -287,6 +287,9 @@ RISC-V TCG CPUs
>   M: Palmer Dabbelt <palmer@dabbelt.com>
>   M: Alistair Francis <alistair.francis@wdc.com>
>   M: Bin Meng <bin.meng@windriver.com>
> +R: Weiwei Li <liweiwei@iscas.ac.cn>
> +R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> +R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>   L: qemu-riscv@nongnu.org
>   S: Supported
>   F: target/riscv/

Frank Chang Feb. 9, 2023, 9:42 a.m. UTC | #6

Reviewed-by: Frank Chang <frank.chang@sifive.com>

On Thu, Feb 9, 2023 at 8:34 AM Alistair Francis <
alistair.francis@opensource.wdc.com> wrote:

> From: Alistair Francis <alistair.francis@wdc.com>
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  MAINTAINERS | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 96e25f62ac..847bc7f131 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -287,6 +287,9 @@ RISC-V TCG CPUs
>  M: Palmer Dabbelt <palmer@dabbelt.com>
>  M: Alistair Francis <alistair.francis@wdc.com>
>  M: Bin Meng <bin.meng@windriver.com>
> +R: Weiwei Li <liweiwei@iscas.ac.cn>
> +R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> +R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>  L: qemu-riscv@nongnu.org
>  S: Supported
>  F: target/riscv/
> --
> 2.39.1
>
>
>

Alistair Francis Feb. 10, 2023, 1:24 a.m. UTC | #7

On Thu, Feb 9, 2023 at 10:33 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  MAINTAINERS | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 96e25f62ac..847bc7f131 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -287,6 +287,9 @@ RISC-V TCG CPUs
>  M: Palmer Dabbelt <palmer@dabbelt.com>
>  M: Alistair Francis <alistair.francis@wdc.com>
>  M: Bin Meng <bin.meng@windriver.com>
> +R: Weiwei Li <liweiwei@iscas.ac.cn>
> +R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> +R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>  L: qemu-riscv@nongnu.org
>  S: Supported
>  F: target/riscv/
> --
> 2.39.1
>

diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..847bc7f131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -287,6 +287,9 @@  RISC-V TCG CPUs
 M: Palmer Dabbelt <palmer@dabbelt.com>
 M: Alistair Francis <alistair.francis@wdc.com>
 M: Bin Meng <bin.meng@windriver.com>
+R: Weiwei Li <liweiwei@iscas.ac.cn>
+R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/