@@ -54,6 +54,11 @@
#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE)
#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS)
+/* UARTCR bits */
+#define PL011_CR_UARTEN (1 << 0)
+#define PL011_CR_TXE (1 << 8)
+#define PL011_CR_RXE (1 << 9)
+
static const unsigned char pl011_id_arm[8] =
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const unsigned char pl011_id_luminary[8] =
@@ -211,6 +216,16 @@ static void pl011_trace_baudrate_change(const PL011State *s)
s->ibrd, s->fbrd);
}
+static inline bool pl011_can_transmit(PL011State *s)
+{
+ return s->cr & PL011_CR_UARTEN && s->cr & PL011_CR_TXE;
+}
+
+static inline bool pl011_can_receive(PL011State *s)
+{
+ return s->cr & PL011_CR_UARTEN && s->cr & PL011_CR_RXE;
+}
+
static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
@@ -221,7 +236,9 @@ static void pl011_write(void *opaque, hwaddr offset,
switch (offset >> 2) {
case 0: /* UARTDR */
- /* ??? Check if transmitter is enabled. */
+ if (!pl011_can_transmit(s)) {
+ break;
+ }
ch = value;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
@@ -287,12 +304,21 @@ static void pl011_write(void *opaque, hwaddr offset,
}
}
-static int pl011_can_receive(void *opaque)
+static int pl011_receive_capacity(void *opaque)
{
PL011State *s = (PL011State *)opaque;
int r;
- r = s->read_count < pl011_get_fifo_depth(s);
+ if (!pl011_can_receive(s)) {
+ r = 0;
+ } else {
+ /*
+ * Capacity is deliberately maxed to 1 here even though we could have
+ * more fifo space. This is something we can optimize, but for now
+ * pl011_receive expects to handle exactly one element at a time.
+ */
+ r = s->read_count < pl011_get_fifo_depth(s);
+ }
trace_pl011_can_receive(s->lcr, s->read_count, r);
return r;
}
@@ -443,7 +469,7 @@ static void pl011_realize(DeviceState *dev, Error **errp)
{
PL011State *s = PL011(dev);
- qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
+ qemu_chr_fe_set_handlers(&s->chr, pl011_receive_capacity, pl011_receive,
pl011_event, NULL, s, NULL, true);
}
@@ -461,7 +487,7 @@ static void pl011_reset(DeviceState *dev)
s->fbrd = 0;
s->read_trigger = 1;
s->ifl = 0x12;
- s->cr = 0x300;
+ s->cr = PL011_CR_RXE | PL011_CR_TXE;
s->flags = 0;
pl011_reset_fifo(s);
}