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Thu, 19 Jan 2023 23:40:29 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.167.38]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Nyry41fh7z1RvLy; Thu, 19 Jan 2023 23:40:28 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Andrew Bresticker , Alistair Francis Subject: [PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 Date: Fri, 20 Jan 2023 17:39:09 +1000 Message-Id: <20230120073913.1028407-34-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> References: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Andrew Bresticker Per the AIA specification, writes to stimecmp from VS level should trap when hvictl.VTI is set since the write may cause vsip.STIP to become unset. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") Signed-off-by: Andrew Bresticker Reviewed-by: Alistair Francis Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 270de7b1a8..62e6c4acbd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1037,6 +1037,9 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, RISCVCPU *cpu = env_archcpu(env); if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } return write_vstimecmp(env, csrno, val); } @@ -1057,6 +1060,9 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, RISCVCPU *cpu = env_archcpu(env); if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } return write_vstimecmph(env, csrno, val); }