@@ -2305,22 +2305,15 @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVException ret;
- uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
+ uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
/* Bring VS-level bits to correct position */
- vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
- new_val &= ~(VS_MODE_INTERRUPTS >> 1);
- new_val |= vsbits << 1;
- vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
- wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
- wr_mask |= vsbits << 1;
+ new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
+ wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
if (ret_val) {
- rval &= mask;
- vsbits = rval & VS_MODE_INTERRUPTS;
- rval &= ~VS_MODE_INTERRUPTS;
- *ret_val = rval | (vsbits >> 1);
+ *ret_val = (rval & mask) >> 1;
}
return ret;
@@ -2521,22 +2514,16 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVException ret;
- uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
+ uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
/* Bring VS-level bits to correct position */
- vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
- new_val &= ~(VS_MODE_INTERRUPTS >> 1);
- new_val |= vsbits << 1;
- vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
- wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
- wr_mask |= vsbits << 1;
-
- ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
+ new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
+ wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
+
+ ret = rmw_mip64(env, csrno, &rval, new_val,
+ wr_mask & mask & vsip_writable_mask);
if (ret_val) {
- rval &= mask;
- vsbits = rval & VS_MODE_INTERRUPTS;
- rval &= ~VS_MODE_INTERRUPTS;
- *ret_val = rval | (vsbits >> 1);
+ *ret_val = (rval & mask) >> 1;
}
return ret;