| Message ID | 20230120070122.3982588-10-armbru@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | [PULL,01/12] coroutine: Clean up superfluous inclusion of qemu/coroutine.h | expand |
Hi Markus, On 20/1/23 08:01, Markus Armbruster wrote: > PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined > in pnv.h. Many users of the header don't actually need them. One > instance is this inclusion loop: hw/ppc/pnv_homer.h includes > hw/ppc/pnv.h for typedef PnvChip, and vice versa for struct PnvHomer. > > Similar structs live in their own headers: PnvHomerClass and PnvHomer > in pnv_homer.h, PnvLpcClass and PnvLpcController in pci_lpc.h, > PnvPsiClass, PnvPsi, Pnv8Psi, Pnv9Psi, Pnv10Psi in pnv_psi.h, ... > > Move PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip to new > pnv_chip.h, and adjust include directives. This breaks the inclusion > loop mentioned above. > > Signed-off-by: Markus Armbruster <armbru@redhat.com> > Reviewed-by: Cédric Le Goater <clg@kaod.org> > Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > Message-Id: <20221222104628.659681-2-armbru@redhat.com> > --- > include/hw/ppc/pnv.h | 143 +----------------------------------- > include/hw/ppc/pnv_chip.h | 147 +++++++++++++++++++++++++++++++++++++ > hw/intc/pnv_xive.c | 1 + > hw/intc/pnv_xive2.c | 1 + > hw/pci-host/pnv_phb3.c | 1 + > hw/pci-host/pnv_phb4_pec.c | 1 + > hw/ppc/pnv.c | 3 + > hw/ppc/pnv_core.c | 1 + > hw/ppc/pnv_homer.c | 1 + > hw/ppc/pnv_lpc.c | 1 + > hw/ppc/pnv_xscom.c | 1 + > 11 files changed, 160 insertions(+), 141 deletions(-) > create mode 100644 include/hw/ppc/pnv_chip.h > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 9ef7e2d0dc..ca49e4281d 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -20,158 +20,19 @@ > #ifndef PPC_PNV_H > #define PPC_PNV_H > > +#include "cpu.h" Why is "cpu.h" required here? For pnv_chip_find_cpu()? Isn't "target/ppc/cpu-qom.h" enough? > #include "hw/boards.h" > #include "hw/sysbus.h" > #include "hw/ipmi/ipmi.h" > -#include "hw/ppc/pnv_lpc.h" > #include "hw/ppc/pnv_pnor.h" > -#include "hw/ppc/pnv_psi.h" > -#include "hw/ppc/pnv_occ.h" > -#include "hw/ppc/pnv_sbe.h" > -#include "hw/ppc/pnv_homer.h" > -#include "hw/ppc/pnv_xive.h" > -#include "hw/ppc/pnv_core.h" > -#include "hw/pci-host/pnv_phb3.h" > -#include "hw/pci-host/pnv_phb4.h" > #include "hw/pci-host/pnv_phb.h" > -#include "qom/object.h" > > #define TYPE_PNV_CHIP "pnv-chip" > -OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, > - PNV_CHIP) > > -struct PnvChip { > - /*< private >*/ > - SysBusDevice parent_obj; > - > - /*< public >*/ > - uint32_t chip_id; > - uint64_t ram_start; > - uint64_t ram_size; > - > - uint32_t nr_cores; > - uint32_t nr_threads; > - uint64_t cores_mask; > - PnvCore **cores; > - > - uint32_t num_pecs; > - > - MemoryRegion xscom_mmio; > - MemoryRegion xscom; > - AddressSpace xscom_as; > - > - MemoryRegion *fw_mr; > - gchar *dt_isa_nodename; > -}; > - > -#define TYPE_PNV8_CHIP "pnv8-chip" > +typedef struct PnvChip PnvChip; > typedef struct Pnv8Chip Pnv8Chip; > -DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, > - TYPE_PNV8_CHIP) > - > -struct Pnv8Chip { > - /*< private >*/ > - PnvChip parent_obj; > - > - /*< public >*/ > - MemoryRegion icp_mmio; > - > - PnvLpcController lpc; > - Pnv8Psi psi; > - PnvOCC occ; > - PnvHomer homer; > - > -#define PNV8_CHIP_PHB3_MAX 4 > - /* > - * The array is used to allow quick access to the phbs by > - * pnv_ics_get_child() and pnv_ics_resend_child(). > - */ > - PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; > - uint32_t num_phbs; > - > - XICSFabric *xics; > -}; > - > -#define TYPE_PNV9_CHIP "pnv9-chip" > typedef struct Pnv9Chip Pnv9Chip; > -DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, > - TYPE_PNV9_CHIP) > - > -struct Pnv9Chip { > - /*< private >*/ > - PnvChip parent_obj; > - > - /*< public >*/ > - PnvXive xive; > - Pnv9Psi psi; > - PnvLpcController lpc; > - PnvOCC occ; > - PnvSBE sbe; > - PnvHomer homer; > - > - uint32_t nr_quads; > - PnvQuad *quads; > - > -#define PNV9_CHIP_MAX_PEC 3 > - PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; > -}; > - > -/* > - * A SMT8 fused core is a pair of SMT4 cores. > - */ > -#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) > -#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) > - > -#define TYPE_PNV10_CHIP "pnv10-chip" > typedef struct Pnv10Chip Pnv10Chip; > -DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, > - TYPE_PNV10_CHIP) > - > -struct Pnv10Chip { > - /*< private >*/ > - PnvChip parent_obj; > - > - /*< public >*/ > - PnvXive2 xive; > - Pnv9Psi psi; > - PnvLpcController lpc; > - PnvOCC occ; > - PnvSBE sbe; > - PnvHomer homer; > - > - uint32_t nr_quads; > - PnvQuad *quads; > - > -#define PNV10_CHIP_MAX_PEC 2 > - PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; > -}; > - > -#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) > -#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) > - > -struct PnvChipClass { > - /*< private >*/ > - SysBusDeviceClass parent_class; > - > - /*< public >*/ > - uint64_t chip_cfam_id; > - uint64_t cores_mask; > - uint32_t num_pecs; > - uint32_t num_phbs; > - > - DeviceRealize parent_realize; > - > - uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); > - void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); > - void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); > - void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); > - void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); > - ISABus *(*isa_create)(PnvChip *chip, Error **errp); > - void (*dt_populate)(PnvChip *chip, void *fdt); > - void (*pic_print_info)(PnvChip *chip, Monitor *mon); > - uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); > - uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); > -}; > > #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP > #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX > diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h > new file mode 100644 > index 0000000000..53e1d921d7 > --- /dev/null > +++ b/include/hw/ppc/pnv_chip.h > @@ -0,0 +1,147 @@ > +#ifndef PPC_PNV_CHIP_H > +#define PPC_PNV_CHIP_H > + > +#include "hw/pci-host/pnv_phb4.h" > +#include "hw/ppc/pnv_core.h" > +#include "hw/ppc/pnv_homer.h" > +#include "hw/ppc/pnv_lpc.h" > +#include "hw/ppc/pnv_occ.h" > +#include "hw/ppc/pnv_psi.h" > +#include "hw/ppc/pnv_sbe.h" > +#include "hw/ppc/pnv_xive.h" > +#include "hw/sysbus.h" > + > +OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, > + PNV_CHIP) > + > +struct PnvChip { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + uint32_t chip_id; > + uint64_t ram_start; > + uint64_t ram_size; > + > + uint32_t nr_cores; > + uint32_t nr_threads; > + uint64_t cores_mask; > + PnvCore **cores; > + > + uint32_t num_pecs; > + > + MemoryRegion xscom_mmio; > + MemoryRegion xscom; > + AddressSpace xscom_as; > + > + MemoryRegion *fw_mr; > + gchar *dt_isa_nodename; > +}; > + > +#define TYPE_PNV8_CHIP "pnv8-chip" > +DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, > + TYPE_PNV8_CHIP) > + > +struct Pnv8Chip { > + /*< private >*/ > + PnvChip parent_obj; > + > + /*< public >*/ > + MemoryRegion icp_mmio; > + > + PnvLpcController lpc; > + Pnv8Psi psi; > + PnvOCC occ; > + PnvHomer homer; > + > +#define PNV8_CHIP_PHB3_MAX 4 > + /* > + * The array is used to allow quick access to the phbs by > + * pnv_ics_get_child() and pnv_ics_resend_child(). > + */ > + PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; > + uint32_t num_phbs; > + > + XICSFabric *xics; > +}; > + > +#define TYPE_PNV9_CHIP "pnv9-chip" > +DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, > + TYPE_PNV9_CHIP) > + > +struct Pnv9Chip { > + /*< private >*/ > + PnvChip parent_obj; > + > + /*< public >*/ > + PnvXive xive; > + Pnv9Psi psi; > + PnvLpcController lpc; > + PnvOCC occ; > + PnvSBE sbe; > + PnvHomer homer; > + > + uint32_t nr_quads; > + PnvQuad *quads; > + > +#define PNV9_CHIP_MAX_PEC 3 > + PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; > +}; > + > +/* > + * A SMT8 fused core is a pair of SMT4 cores. > + */ > +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) > +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) > + > +#define TYPE_PNV10_CHIP "pnv10-chip" > +DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, > + TYPE_PNV10_CHIP) > + > +struct Pnv10Chip { > + /*< private >*/ > + PnvChip parent_obj; > + > + /*< public >*/ > + PnvXive2 xive; > + Pnv9Psi psi; > + PnvLpcController lpc; > + PnvOCC occ; > + PnvSBE sbe; > + PnvHomer homer; > + > + uint32_t nr_quads; > + PnvQuad *quads; > + > +#define PNV10_CHIP_MAX_PEC 2 > + PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; > +}; > + > +#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) > +#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) > + > +struct PnvChipClass { > + /*< private >*/ > + SysBusDeviceClass parent_class; > + > + /*< public >*/ > + uint64_t chip_cfam_id; > + uint64_t cores_mask; > + uint32_t num_pecs; > + uint32_t num_phbs; > + > + DeviceRealize parent_realize; > + > + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); > + void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); > + void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); > + void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); > + void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); > + ISABus *(*isa_create)(PnvChip *chip, Error **errp); > + void (*dt_populate)(PnvChip *chip, void *fdt); > + void (*pic_print_info)(PnvChip *chip, Monitor *mon); > + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); > + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); > +}; > + > +#endif
Philippe Mathieu-Daudé <philmd@linaro.org> writes: > Hi Markus, > > On 20/1/23 08:01, Markus Armbruster wrote: >> PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined >> in pnv.h. Many users of the header don't actually need them. One >> instance is this inclusion loop: hw/ppc/pnv_homer.h includes >> hw/ppc/pnv.h for typedef PnvChip, and vice versa for struct PnvHomer. >> Similar structs live in their own headers: PnvHomerClass and PnvHomer >> in pnv_homer.h, PnvLpcClass and PnvLpcController in pci_lpc.h, >> PnvPsiClass, PnvPsi, Pnv8Psi, Pnv9Psi, Pnv10Psi in pnv_psi.h, ... >> Move PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip to new >> pnv_chip.h, and adjust include directives. This breaks the inclusion >> loop mentioned above. >> Signed-off-by: Markus Armbruster <armbru@redhat.com> >> Reviewed-by: Cédric Le Goater <clg@kaod.org> >> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> >> Message-Id: <20221222104628.659681-2-armbru@redhat.com> >> --- >> include/hw/ppc/pnv.h | 143 +----------------------------------- >> include/hw/ppc/pnv_chip.h | 147 +++++++++++++++++++++++++++++++++++++ >> hw/intc/pnv_xive.c | 1 + >> hw/intc/pnv_xive2.c | 1 + >> hw/pci-host/pnv_phb3.c | 1 + >> hw/pci-host/pnv_phb4_pec.c | 1 + >> hw/ppc/pnv.c | 3 + >> hw/ppc/pnv_core.c | 1 + >> hw/ppc/pnv_homer.c | 1 + >> hw/ppc/pnv_lpc.c | 1 + >> hw/ppc/pnv_xscom.c | 1 + >> 11 files changed, 160 insertions(+), 141 deletions(-) >> create mode 100644 include/hw/ppc/pnv_chip.h >> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h >> index 9ef7e2d0dc..ca49e4281d 100644 >> --- a/include/hw/ppc/pnv.h >> +++ b/include/hw/ppc/pnv.h >> @@ -20,158 +20,19 @@ >> #ifndef PPC_PNV_H >> #define PPC_PNV_H >> +#include "cpu.h" > > Why is "cpu.h" required here? For pnv_chip_find_cpu()? Yes: ../include/hw/ppc/pnv.h:58:1: error: unknown type name ‘PowerPCCPU’ 58 | PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); | ^~~~~~~~~~ > Isn't "target/ppc/cpu-qom.h" enough? Seems to suffice. Would you like to post a followup?
On 23/1/23 11:07, Markus Armbruster wrote: > Philippe Mathieu-Daudé <philmd@linaro.org> writes: > >> Hi Markus, >> >> On 20/1/23 08:01, Markus Armbruster wrote: >>> PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined >>> in pnv.h. Many users of the header don't actually need them. One >>> instance is this inclusion loop: hw/ppc/pnv_homer.h includes >>> hw/ppc/pnv.h for typedef PnvChip, and vice versa for struct PnvHomer. >>> Similar structs live in their own headers: PnvHomerClass and PnvHomer >>> in pnv_homer.h, PnvLpcClass and PnvLpcController in pci_lpc.h, >>> PnvPsiClass, PnvPsi, Pnv8Psi, Pnv9Psi, Pnv10Psi in pnv_psi.h, ... >>> Move PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip to new >>> pnv_chip.h, and adjust include directives. This breaks the inclusion >>> loop mentioned above. >>> Signed-off-by: Markus Armbruster <armbru@redhat.com> >>> Reviewed-by: Cédric Le Goater <clg@kaod.org> >>> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> >>> Message-Id: <20221222104628.659681-2-armbru@redhat.com> >>> --- >>> include/hw/ppc/pnv.h | 143 +----------------------------------- >>> include/hw/ppc/pnv_chip.h | 147 +++++++++++++++++++++++++++++++++++++ >>> hw/intc/pnv_xive.c | 1 + >>> hw/intc/pnv_xive2.c | 1 + >>> hw/pci-host/pnv_phb3.c | 1 + >>> hw/pci-host/pnv_phb4_pec.c | 1 + >>> hw/ppc/pnv.c | 3 + >>> hw/ppc/pnv_core.c | 1 + >>> hw/ppc/pnv_homer.c | 1 + >>> hw/ppc/pnv_lpc.c | 1 + >>> hw/ppc/pnv_xscom.c | 1 + >>> 11 files changed, 160 insertions(+), 141 deletions(-) >>> create mode 100644 include/hw/ppc/pnv_chip.h >>> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h >>> index 9ef7e2d0dc..ca49e4281d 100644 >>> --- a/include/hw/ppc/pnv.h >>> +++ b/include/hw/ppc/pnv.h >>> @@ -20,158 +20,19 @@ >>> #ifndef PPC_PNV_H >>> #define PPC_PNV_H >>> +#include "cpu.h" >> >> Why is "cpu.h" required here? For pnv_chip_find_cpu()? > > Yes: > > ../include/hw/ppc/pnv.h:58:1: error: unknown type name ‘PowerPCCPU’ > 58 | PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); > | ^~~~~~~~~~ > >> Isn't "target/ppc/cpu-qom.h" enough? > > Seems to suffice. Would you like to post a followup? Good. First I need to finish the ARM part and deal with this comment: https://lore.kernel.org/qemu-devel/325310d0-aad6-fc39-748a-80762d644dd8@linaro.org/ Then this change will be included in the PPC equivalent series. Thanks, Phil.
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 9ef7e2d0dc..ca49e4281d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -20,158 +20,19 @@ #ifndef PPC_PNV_H #define PPC_PNV_H +#include "cpu.h" #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/ipmi/ipmi.h" -#include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_pnor.h" -#include "hw/ppc/pnv_psi.h" -#include "hw/ppc/pnv_occ.h" -#include "hw/ppc/pnv_sbe.h" -#include "hw/ppc/pnv_homer.h" -#include "hw/ppc/pnv_xive.h" -#include "hw/ppc/pnv_core.h" -#include "hw/pci-host/pnv_phb3.h" -#include "hw/pci-host/pnv_phb4.h" #include "hw/pci-host/pnv_phb.h" -#include "qom/object.h" #define TYPE_PNV_CHIP "pnv-chip" -OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, - PNV_CHIP) -struct PnvChip { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - uint32_t chip_id; - uint64_t ram_start; - uint64_t ram_size; - - uint32_t nr_cores; - uint32_t nr_threads; - uint64_t cores_mask; - PnvCore **cores; - - uint32_t num_pecs; - - MemoryRegion xscom_mmio; - MemoryRegion xscom; - AddressSpace xscom_as; - - MemoryRegion *fw_mr; - gchar *dt_isa_nodename; -}; - -#define TYPE_PNV8_CHIP "pnv8-chip" +typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; -DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, - TYPE_PNV8_CHIP) - -struct Pnv8Chip { - /*< private >*/ - PnvChip parent_obj; - - /*< public >*/ - MemoryRegion icp_mmio; - - PnvLpcController lpc; - Pnv8Psi psi; - PnvOCC occ; - PnvHomer homer; - -#define PNV8_CHIP_PHB3_MAX 4 - /* - * The array is used to allow quick access to the phbs by - * pnv_ics_get_child() and pnv_ics_resend_child(). - */ - PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; - uint32_t num_phbs; - - XICSFabric *xics; -}; - -#define TYPE_PNV9_CHIP "pnv9-chip" typedef struct Pnv9Chip Pnv9Chip; -DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, - TYPE_PNV9_CHIP) - -struct Pnv9Chip { - /*< private >*/ - PnvChip parent_obj; - - /*< public >*/ - PnvXive xive; - Pnv9Psi psi; - PnvLpcController lpc; - PnvOCC occ; - PnvSBE sbe; - PnvHomer homer; - - uint32_t nr_quads; - PnvQuad *quads; - -#define PNV9_CHIP_MAX_PEC 3 - PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; -}; - -/* - * A SMT8 fused core is a pair of SMT4 cores. - */ -#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) - -#define TYPE_PNV10_CHIP "pnv10-chip" typedef struct Pnv10Chip Pnv10Chip; -DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, - TYPE_PNV10_CHIP) - -struct Pnv10Chip { - /*< private >*/ - PnvChip parent_obj; - - /*< public >*/ - PnvXive2 xive; - Pnv9Psi psi; - PnvLpcController lpc; - PnvOCC occ; - PnvSBE sbe; - PnvHomer homer; - - uint32_t nr_quads; - PnvQuad *quads; - -#define PNV10_CHIP_MAX_PEC 2 - PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; -}; - -#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) - -struct PnvChipClass { - /*< private >*/ - SysBusDeviceClass parent_class; - - /*< public >*/ - uint64_t chip_cfam_id; - uint64_t cores_mask; - uint32_t num_pecs; - uint32_t num_phbs; - - DeviceRealize parent_realize; - - uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); - void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); - void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); - void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); - void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); - ISABus *(*isa_create)(PnvChip *chip, Error **errp); - void (*dt_populate)(PnvChip *chip, void *fdt); - void (*pic_print_info)(PnvChip *chip, Monitor *mon); - uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); - uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); -}; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h new file mode 100644 index 0000000000..53e1d921d7 --- /dev/null +++ b/include/hw/ppc/pnv_chip.h @@ -0,0 +1,147 @@ +#ifndef PPC_PNV_CHIP_H +#define PPC_PNV_CHIP_H + +#include "hw/pci-host/pnv_phb4.h" +#include "hw/ppc/pnv_core.h" +#include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_lpc.h" +#include "hw/ppc/pnv_occ.h" +#include "hw/ppc/pnv_psi.h" +#include "hw/ppc/pnv_sbe.h" +#include "hw/ppc/pnv_xive.h" +#include "hw/sysbus.h" + +OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, + PNV_CHIP) + +struct PnvChip { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + uint32_t chip_id; + uint64_t ram_start; + uint64_t ram_size; + + uint32_t nr_cores; + uint32_t nr_threads; + uint64_t cores_mask; + PnvCore **cores; + + uint32_t num_pecs; + + MemoryRegion xscom_mmio; + MemoryRegion xscom; + AddressSpace xscom_as; + + MemoryRegion *fw_mr; + gchar *dt_isa_nodename; +}; + +#define TYPE_PNV8_CHIP "pnv8-chip" +DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, + TYPE_PNV8_CHIP) + +struct Pnv8Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ + MemoryRegion icp_mmio; + + PnvLpcController lpc; + Pnv8Psi psi; + PnvOCC occ; + PnvHomer homer; + +#define PNV8_CHIP_PHB3_MAX 4 + /* + * The array is used to allow quick access to the phbs by + * pnv_ics_get_child() and pnv_ics_resend_child(). + */ + PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; + uint32_t num_phbs; + + XICSFabric *xics; +}; + +#define TYPE_PNV9_CHIP "pnv9-chip" +DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, + TYPE_PNV9_CHIP) + +struct Pnv9Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ + PnvXive xive; + Pnv9Psi psi; + PnvLpcController lpc; + PnvOCC occ; + PnvSBE sbe; + PnvHomer homer; + + uint32_t nr_quads; + PnvQuad *quads; + +#define PNV9_CHIP_MAX_PEC 3 + PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; +}; + +/* + * A SMT8 fused core is a pair of SMT4 cores. + */ +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) + +#define TYPE_PNV10_CHIP "pnv10-chip" +DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, + TYPE_PNV10_CHIP) + +struct Pnv10Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ + PnvXive2 xive; + Pnv9Psi psi; + PnvLpcController lpc; + PnvOCC occ; + PnvSBE sbe; + PnvHomer homer; + + uint32_t nr_quads; + PnvQuad *quads; + +#define PNV10_CHIP_MAX_PEC 2 + PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; +}; + +#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) + +struct PnvChipClass { + /*< private >*/ + SysBusDeviceClass parent_class; + + /*< public >*/ + uint64_t chip_cfam_id; + uint64_t cores_mask; + uint32_t num_pecs; + uint32_t num_phbs; + + DeviceRealize parent_realize; + + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); + void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); + void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); + ISABus *(*isa_create)(PnvChip *chip, Error **errp); + void (*dt_populate)(PnvChip *chip, void *fdt); + void (*pic_print_info)(PnvChip *chip, Monitor *mon); + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); +}; + +#endif diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index c7b75ed12e..622f9d28b7 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -18,6 +18,7 @@ #include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_xive.h" diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index f22ce5ca59..7176d70234 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -16,6 +16,7 @@ #include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xive2.h" diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 9054c393a2..7a21497cf8 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -16,6 +16,7 @@ #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qom/object.h" diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 9871f462cd..43267a428f 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -17,6 +17,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3d01e26f84..44b1fbbc93 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -44,9 +44,12 @@ #include "target/ppc/mmu-hash64.h" #include "hw/pci/msi.h" #include "hw/pci-host/pnv_phb.h" +#include "hw/pci-host/pnv_phb3.h" +#include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_pnor.h" diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 9ee79192dd..410f31bdf8 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -25,6 +25,7 @@ #include "target/ppc/cpu.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index ea73919e54..f9a203d11d 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -25,6 +25,7 @@ #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_xscom.h" diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index ee890e7ab4..71143b7692 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -26,6 +26,7 @@ #include "hw/isa/isa.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/fdt.h" diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 79f10de57f..d820e05e40 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -26,6 +26,7 @@ #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_xscom.h" #include <libfdt.h>