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Tue, 10 Jan 2023 09:39:29 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 272A11FFC8; Tue, 10 Jan 2023 17:39:25 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Alexandre Iooss , Beraldo Leal , Thomas Huth , John Snow , Eduardo Habkost , Elena Ufimtseva , Ed Maste , Yanan Wang , Cleber Rosa , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Li-Wen Hsu , Markus Armbruster , Jagannathan Raman , =?utf-8?q?Daniel_P=2E_Berrang?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Michael Roth , Wainer dos Santos Moschetta , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , qemu-arm@nongnu.org, Marcel Apfelbaum , Peter Maydell , Paolo Bonzini , Mahmoud Mandour , John G Johnson , Robert Henry , Aaron Lindsay Subject: [PATCH 17/26] tests/tcg: add memory-sve test for aarch64 Date: Tue, 10 Jan 2023 17:39:13 +0000 Message-Id: <20230110173922.265055-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230110173922.265055-1-alex.bennee@linaro.org> References: <20230110173922.265055-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This will be helpful in debugging problems with tracking SVE memory accesses via the TCG plugins system. Signed-off-by: Alex Bennée Cc: Robert Henry Cc: Aaron Lindsay Reviewed-by: Richard Henderson --- tests/tcg/aarch64/Makefile.softmmu-target | 7 +++++++ tests/tcg/aarch64/system/boot.S | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index a1368905f5..df9747bae8 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -36,6 +36,13 @@ config-cc.mak: Makefile memory: CFLAGS+=-DCHECK_UNALIGNED=1 +memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + +memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3 -fno-tree-loop-distribute-patterns + +TESTS+=memory-sve + # Running QEMU_BASE_MACHINE=-M virt -cpu max -display none QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S index e190b1efa6..f136363d2a 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -179,12 +179,13 @@ __start: isb /* - * Enable FP registers. The standard C pre-amble will be + * Enable FP/SVE registers. The standard C pre-amble will be * saving these and A-profile compilers will use AdvSIMD * registers unless we tell it not to. */ mrs x0, cpacr_el1 orr x0, x0, #(3 << 20) + orr x0, x0, #(3 << 16) msr cpacr_el1, x0 /* Setup some stack space and enter the test code.