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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/34] hw/timer/imx_epit: define SR_OCIF Date: Thu, 5 Jan 2023 16:43:55 +0000 Message-Id: <20230105164417.3994639-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 2 ++ hw/timer/imx_epit.c | 12 ++++++------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index e2cb96229be..783eaf0c3a6 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -53,6 +53,8 @@ #define CR_CLKSRC_SHIFT (24) #define CR_CLKSRC_BITS (2) +#define SR_OCIF (1 << 0) + #define EPIT_TIMER_MAX 0XFFFFFFFFUL #define TYPE_IMX_EPIT "imx.epit" diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 661e9158e3b..f148868b8cb 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -66,7 +66,7 @@ static const IMXClk imx_epit_clocks[] = { */ static void imx_epit_update_int(IMXEPITState *s) { - if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { + if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { qemu_irq_raise(s->irq); } else { qemu_irq_lower(s->irq); @@ -256,9 +256,9 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, break; case 1: /* SR - ACK*/ - /* writing 1 to OCIF clears the OCIF bit */ - if (value & 0x01) { - s->sr = 0; + /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ + if (value & SR_OCIF) { + s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ imx_epit_update_int(s); } break; @@ -309,8 +309,8 @@ static void imx_epit_cmp(void *opaque) IMXEPITState *s = IMX_EPIT(opaque); DPRINTF("sr was %d\n", s->sr); - - s->sr = 1; + /* Set interrupt status bit SR.OCIF and update the interrupt state */ + s->sr |= SR_OCIF; imx_epit_update_int(s); }