| Message ID | 20221229152325.32041-8-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/aspeed_ast10x0: Map more peripherals & few more fixes | expand |
On Thu, Dec 29, 2022 at 04:23:23PM +0100, Philippe Mathieu-Daudé wrote: > address_space_map() can fail: > > uart:~$ hash test > sha256_test > tv[0]: > Segmentation fault: 11 > Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault. > gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0) > at ../hw/misc/aspeed_hace.c:171 > 171 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) { > (gdb) bt > #0 gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0) > at ../hw/misc/aspeed_hace.c:171 > #1 do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true) > at ../hw/misc/aspeed_hace.c:224 > #2 0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>) > at ../hw/misc/aspeed_hace.c:358 > > This change doesn't fix much, but at least the guest > can't crash QEMU anymore. Instead it is still usable: > > uart:~$ hash test > sha256_test > tv[0]:hash_final error > sha384_test > tv[0]:hash_final error > sha512_test > tv[0]:hash_final error > [00:00:06.278,000] <err> hace_global: HACE poll timeout > [00:00:09.324,000] <err> hace_global: HACE poll timeout > [00:00:12.261,000] <err> hace_global: HACE poll timeout > uart:~$ > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Good catch, Reviewed-by: Peter Delevoryas <peter@pjd.dev> Maybe include this tag? Fixes: c5475b3f9a ("hw: Model ASPEED's Hash and Crypto Engine") > --- > hw/misc/aspeed_hace.c | 21 +++++++++++++++------ > 1 file changed, 15 insertions(+), 6 deletions(-) > > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c > index ac21be306c..12a761f1f5 100644 > --- a/hw/misc/aspeed_hace.c > +++ b/hw/misc/aspeed_hace.c > @@ -193,6 +193,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > size_t digest_len = 0; > int niov = 0; > int i; > + void *haddr; > > if (sg_mode) { > uint32_t len = 0; > @@ -217,9 +218,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > addr &= SG_LIST_ADDR_MASK; > > plen = len & SG_LIST_LEN_MASK; > - iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, > - MEMTXATTRS_UNSPECIFIED); > - > + haddr = address_space_map(&s->dram_as, addr, &plen, false, > + MEMTXATTRS_UNSPECIFIED); > + if (haddr == NULL) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); > + return; > + } > + iov[i].iov_base = haddr; > if (acc_mode) { > niov = gen_acc_mode_iov(s, iov, i, &plen); > > @@ -230,10 +235,14 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, > } else { > hwaddr len = s->regs[R_HASH_SRC_LEN]; > > + haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], > + &len, false, MEMTXATTRS_UNSPECIFIED); > + if (haddr == NULL) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); > + return; > + } > + iov[0].iov_base = haddr; > iov[0].iov_len = len; > - iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], > - &len, false, > - MEMTXATTRS_UNSPECIFIED); > i = 1; > > if (s->iov_count) { > -- > 2.38.1 >
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index ac21be306c..12a761f1f5 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -193,6 +193,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, size_t digest_len = 0; int niov = 0; int i; + void *haddr; if (sg_mode) { uint32_t len = 0; @@ -217,9 +218,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, addr &= SG_LIST_ADDR_MASK; plen = len & SG_LIST_LEN_MASK; - iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, - MEMTXATTRS_UNSPECIFIED); - + haddr = address_space_map(&s->dram_as, addr, &plen, false, + MEMTXATTRS_UNSPECIFIED); + if (haddr == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + iov[i].iov_base = haddr; if (acc_mode) { niov = gen_acc_mode_iov(s, iov, i, &plen); @@ -230,10 +235,14 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, } else { hwaddr len = s->regs[R_HASH_SRC_LEN]; + haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], + &len, false, MEMTXATTRS_UNSPECIFIED); + if (haddr == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + iov[0].iov_base = haddr; iov[0].iov_len = len; - iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], - &len, false, - MEMTXATTRS_UNSPECIFIED); i = 1; if (s->iov_count) {
address_space_map() can fail: uart:~$ hash test sha256_test tv[0]: Segmentation fault: 11 Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault. gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0) at ../hw/misc/aspeed_hace.c:171 171 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) { (gdb) bt #0 gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0) at ../hw/misc/aspeed_hace.c:171 #1 do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true) at ../hw/misc/aspeed_hace.c:224 #2 0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>) at ../hw/misc/aspeed_hace.c:358 This change doesn't fix much, but at least the guest can't crash QEMU anymore. Instead it is still usable: uart:~$ hash test sha256_test tv[0]:hash_final error sha384_test tv[0]:hash_final error sha512_test tv[0]:hash_final error [00:00:06.278,000] <err> hace_global: HACE poll timeout [00:00:09.324,000] <err> hace_global: HACE poll timeout [00:00:12.261,000] <err> hace_global: HACE poll timeout uart:~$ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/misc/aspeed_hace.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-)