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Wed, 28 Dec 2022 15:37:16 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BSFbFkS029693 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 28 Dec 2022 15:37:15 GMT Received: from mthiyaga-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 28 Dec 2022 07:37:13 -0800 From: Mukilan Thiyagarajan To: , CC: , , Mukilan Thiyagarajan Subject: [PATCH] tests/tcg/hexagon: fix underspecifed asm constraints Date: Wed, 28 Dec 2022 21:06:57 +0530 Message-ID: <20221228153657.10210-1-quic_mthiyaga@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2y_1ofmeQXtA2wrbltlV6BMDeJ2HBmuy X-Proofpoint-ORIG-GUID: 2y_1ofmeQXtA2wrbltlV6BMDeJ2HBmuy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-28_12,2022-12-28_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 adultscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212280134 Received-SPF: pass client-ip=205.220.168.131; envelope-from=quic_mthiyaga@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There are two test cases where the inline asm doesn't have the correct constraints causing them to fail when using certain clang versions/optimization levels. In mem_noshuf.c, the register r7 is written to but not specified in the clobber list. In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register. Signed-off-by: Mukilan Thiyagarajan Reviewed-by: Taylor Simpson Reviewed-by: Taylor Simpson --- tests/tcg/hexagon/mem_noshuf.c | 2 +- tests/tcg/hexagon/misc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/tcg/hexagon/mem_noshuf.c b/tests/tcg/hexagon/mem_noshuf.c index 0f4064e700..210b2f1208 100644 --- a/tests/tcg/hexagon/mem_noshuf.c +++ b/tests/tcg/hexagon/mem_noshuf.c @@ -144,7 +144,7 @@ static inline long long pred_ld_sd_pi(int pred, long long *p, long long *q, "}:mem_noshuf\n" : "=&r"(ret) : "r"(p), "r"(q), "r"(x), "r"(y), "r"(pred) - : "p0", "memory"); + : "r7", "p0", "memory"); return ret; } diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index f0b1947fb3..9b1604d82f 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -189,7 +189,7 @@ static int L2_ploadrifnew_pi(void *p, int pred) " p0 = cmp.eq(%1, #1)\n\t" " if (!p0.new) %0 = memw(%2++#4)\n\t" "}\n\t" - : "=r"(result) : "r"(pred), "r"(p) + : "=&r"(result) : "r"(pred), "r"(p) : "p0"); return result; }