| Message ID | 20221228124242.184784-2-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: opensbi boot test and cleanups | expand |
On 28/12/22 13:42, Daniel Henrique Barboza wrote: > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > The riscv32 'spike' machine isn't bootable at this moment, requiring an > Opensbi fix [1] and QEMU side changes [2]. We could just leave at that > or add a 'skip' test to remind us about it. To work as a reminder that > we have a riscv32 'spike' test that should be enabled as soon as Opensbi > QEMU rom receives the fix, we're adding a 'skip' test: > > (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: > SKIP: requires OpenSBI fix to work > > [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/ > [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 > > Cc: Cleber Rosa <crosa@redhat.com> > Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > new file mode 100644 > index 0000000000..64fcf3c774 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,77 @@ > +# opensbi boot test for RISC-V machines s/opensbi/OpenSBI/ > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado import skip > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=accel:tcg > + """ > + timeout = 5 Easier to review common code once: def boot_opensbi(self): self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, 'Platform Name') wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:virt > + """ self.boot_opensbi() > + def test_riscv64_spike(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:spike > + """ self.boot_opensbi() [...] > + @skip("requires OpenSBI fix to work") > + def test_riscv32_spike(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:spike > + """ self.boot_opensbi()
On 12/28/22 09:59, Philippe Mathieu-Daudé wrote: > On 28/12/22 13:42, Daniel Henrique Barboza wrote: >> This test is used to do a quick sanity check to ensure that we're able >> to run the existing QEMU FW image. >> >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | >> RISCV32_BIOS_BIN firmware with minimal options. >> >> The riscv32 'spike' machine isn't bootable at this moment, requiring an >> Opensbi fix [1] and QEMU side changes [2]. We could just leave at that >> or add a 'skip' test to remind us about it. To work as a reminder that >> we have a riscv32 'spike' test that should be enabled as soon as Opensbi >> QEMU rom receives the fix, we're adding a 'skip' test: >> >> (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: >> SKIP: requires OpenSBI fix to work >> >> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/ >> [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 >> >> Cc: Cleber Rosa <crosa@redhat.com> >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> --- >> tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 tests/avocado/riscv_opensbi.py >> >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py >> new file mode 100644 >> index 0000000000..64fcf3c774 >> --- /dev/null >> +++ b/tests/avocado/riscv_opensbi.py >> @@ -0,0 +1,77 @@ >> +# opensbi boot test for RISC-V machines > > s/opensbi/OpenSBI/ > >> +# >> +# Copyright (c) 2022, Ventana Micro >> +# >> +# This work is licensed under the terms of the GNU GPL, version 2 or >> +# later. See the COPYING file in the top-level directory. >> + >> +from avocado_qemu import QemuSystemTest >> +from avocado import skip >> +from avocado_qemu import wait_for_console_pattern >> + >> +class RiscvOpensbi(QemuSystemTest): >> + """ >> + :avocado: tags=accel:tcg >> + """ >> + timeout = 5 > > Easier to review common code once: > > def boot_opensbi(self): > self.vm.set_console() > self.vm.launch() > wait_for_console_pattern(self, 'Platform Name') > wait_for_console_pattern(self, 'Boot HART MEDELEG') Yeah I mean, here I am, adding duplicated logic in a series that was aimed to reduce duplicated logic :D I'll refactor it in v3. Thanks! Daniel > >> + >> + def test_riscv64_virt(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:virt >> + """ > > self.boot_opensbi() > >> + def test_riscv64_spike(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:spike >> + """ > > self.boot_opensbi() > > [...] > >> + @skip("requires OpenSBI fix to work") >> + def test_riscv32_spike(self): >> + """ >> + :avocado: tags=arch:riscv32 >> + :avocado: tags=machine:spike >> + """ > > self.boot_opensbi() > >
diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py new file mode 100644 index 0000000000..64fcf3c774 --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,77 @@ +# opensbi boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado import skip +from avocado_qemu import wait_for_console_pattern + +class RiscvOpensbi(QemuSystemTest): + """ + :avocado: tags=accel:tcg + """ + timeout = 5 + + def test_riscv64_virt(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:virt + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_spike(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:spike + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:sifive_u + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv32_virt(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:virt + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:sifive_u + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + @skip("requires OpenSBI fix to work") + def test_riscv32_spike(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:spike + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG')
This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. The riscv32 'spike' machine isn't bootable at this moment, requiring an Opensbi fix [1] and QEMU side changes [2]. We could just leave at that or add a 'skip' test to remind us about it. To work as a reminder that we have a riscv32 'spike' test that should be enabled as soon as Opensbi QEMU rom receives the fix, we're adding a 'skip' test: (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: SKIP: requires OpenSBI fix to work [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/ [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 Cc: Cleber Rosa <crosa@redhat.com> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py