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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a05600c364700b003d33ab317dasm4135263wmq.14.2022.12.16.13.43.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:43:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/36] target/openrisc: Convert to 3-phase reset Date: Fri, 16 Dec 2022 21:42:30 +0000 Message-Id: <20221216214244.1391647-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216214244.1391647-1-peter.maydell@linaro.org> References: <20221216214244.1391647-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the openrisc CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Cédric Le Goater Reviewed-by: Edgar E. Iglesias Reviewed-by: Taylor Simpson Message-id: 20221124115023.2437291-13-peter.maydell@linaro.org --- target/openrisc/cpu.h | 4 ++-- target/openrisc/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1d5efa5ca2f..5f607497052 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A OpenRISC CPU model. */ @@ -44,7 +44,7 @@ struct OpenRISCCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; #define TARGET_INSN_START_EXTRA_WORDS 1 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index de0176cd20c..4c11a1f7ada 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -70,13 +70,15 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) info->print_insn = print_insn_or1k; } -static void openrisc_cpu_reset(DeviceState *dev) +static void openrisc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); OpenRISCCPU *cpu = OPENRISC_CPU(s); OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); - occ->parent_reset(dev); + if (occ->parent_phases.hold) { + occ->parent_phases.hold(obj); + } memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); @@ -229,10 +231,12 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(occ); DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); + resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, + &occ->parent_phases); cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work;