diff mbox series

[v2,14/27] target/s390x: Assert masking of psw.addr in cpu_get_tb_cpu_state

Message ID 20221211152802.923900-15-richard.henderson@linaro.org
State New
Headers show
Series target/s390x: pc-relative translation blocks | expand

Commit Message

Richard Henderson Dec. 11, 2022, 3:27 p.m. UTC 
When changing modes via SAM, we raise a specification exception if the
new PC is out of range.  The masking in s390x_tr_init_disas_context
was too late to be correct, but may be removed.  Add a debugging
assert in cpu_get_tb_cpu_state.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/s390x/cpu.h           | 20 ++++++++++++++------
 target/s390x/tcg/translate.c |  6 +-----
 2 files changed, 15 insertions(+), 11 deletions(-)

Comments

Ilya Leoshkevich Dec. 13, 2022, 5:14 p.m. UTC | #1 
On Sun, Dec 11, 2022 at 09:27:49AM -0600, Richard Henderson wrote:
> When changing modes via SAM, we raise a specification exception if the
> new PC is out of range.  The masking in s390x_tr_init_disas_context
> was too late to be correct, but may be removed.  Add a debugging
> assert in cpu_get_tb_cpu_state.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/s390x/cpu.h           | 20 ++++++++++++++------
>  target/s390x/tcg/translate.c |  6 +-----
>  2 files changed, 15 insertions(+), 11 deletions(-)

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
diff mbox series

Patch

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7d6d01325b..c7eeebfc53 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -379,17 +379,25 @@  static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 }
 
 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
-                                        target_ulong *cs_base, uint32_t *flags)
+                                        target_ulong *cs_base, uint32_t *pflags)
 {
-    *pc = env->psw.addr;
-    *cs_base = env->ex_value;
-    *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+    int flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
     if (env->cregs[0] & CR0_AFP) {
-        *flags |= FLAG_MASK_AFP;
+        flags |= FLAG_MASK_AFP;
     }
     if (env->cregs[0] & CR0_VECTOR) {
-        *flags |= FLAG_MASK_VECTOR;
+        flags |= FLAG_MASK_VECTOR;
     }
+    *pflags = flags;
+    *cs_base = env->ex_value;
+    *pc = env->psw.addr;
+#ifdef CONFIG_DEBUG_TCG
+    if (!(flags & FLAG_MASK_32)) {
+        assert(*pc <= 0xffffff);
+    } else if (!(flags & FLAG_MASK_64)) {
+        assert(*pc <= 0x7fffffff);
+    }
+#endif
 }
 
 /* PER bits from control register 9 */
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index c9afa28c60..fcf0c52b8d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6491,11 +6491,7 @@  static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
 
-    /* 31-bit mode */
-    if (!(dc->base.tb->flags & FLAG_MASK_64)) {
-        dc->base.pc_first &= 0x7fffffff;
-        dc->base.pc_next = dc->base.pc_first;
-    }
+    /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */
 
     dc->cc_op = CC_OP_DYNAMIC;
     dc->ex_value = dc->base.tb->cs_base;