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Fri, 09 Dec 2022 07:15:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Thomas Huth , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-8.0 4/7] hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property Date: Fri, 9 Dec 2022 16:15:30 +0100 Message-Id: <20221209151533.69516-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209151533.69516-1-philmd@linaro.org> References: <20221209151533.69516-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Philippe Mathieu-Daudé This device does not have to be TARGET-dependent. Add a 'cpu_big_endian' property which sets the byte-swapping options if required. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 8c9ec80f7c..9ae4953d1e 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "qemu/log.h" +#include "hw/qdev-properties.h" #include "hw/registerfields.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" @@ -242,6 +243,8 @@ FIELD(GT_PCI1_CMD, SByteSwap, 16, 1) OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE) +#define FEAT_CPU_LE 0 + struct GT64120State { PCIHostState parent_obj; @@ -252,6 +255,9 @@ struct GT64120State { PCI_MAPPING_ENTRY(ISD); MemoryRegion pci0_mem; AddressSpace pci0_mem_as; + + /* properties */ + uint32_t features; }; /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -994,11 +1000,7 @@ static const MemoryRegionOps isd_mem_ops = { static void gt64120_reset(DeviceState *dev) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); -#if TARGET_BIG_ENDIAN - unsigned cpu_le = 0; -#else - unsigned cpu_le = 1; -#endif + unsigned cpu_le = extract32(s->features, FEAT_CPU_LE, 1); /* FIXME: Malta specific hw assumptions ahead */ @@ -1229,11 +1231,18 @@ static const TypeInfo gt64120_pci_info = { }, }; +static Property gt64120_properties[] = { + DEFINE_PROP_BIT("cpu-little-endian", GT64120State, + features, FEAT_CPU_LE, !TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + static void gt64120_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + device_class_set_props(dc, gt64120_properties); dc->realize = gt64120_realize; dc->reset = gt64120_reset; dc->vmsd = &vmstate_gt64120;