From patchwork Wed Dec 7 10:03:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1713202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NRtNZ4tM1z23pB for ; Wed, 7 Dec 2022 21:11:26 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p2rI4-0004kN-39; Wed, 07 Dec 2022 05:04:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p2rI2-0004j4-6z; Wed, 07 Dec 2022 05:04:34 -0500 Received: from bg4.exmail.qq.com ([43.154.221.58]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p2rI0-0006UC-AO; Wed, 07 Dec 2022 05:04:33 -0500 X-QQ-mid: bizesmtp63t1670407458tegefy8m Received: from ubuntu.. ( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 07 Dec 2022 18:04:17 +0800 (CST) X-QQ-SSF: 01200000000000B0B000000A0000000 X-QQ-FEAT: tPxzKmGTl1fnsnfyBR9WcvevjLi3y08N81UP6kTeifl5f4Fdn5+tTS7DuPmKm BiIDdULhT4crm3Et2bJBYhIUfORzEoDYBvn0xyR3vSLweoNPnQosSYzxxtFePiqeXtKFJC3 fxYWUb0HlwvOoQQBlS363cEu+XEHIAnuJftEaggCcaQlQCWrFNa+Sv/89J6ZFt+THn+B1N1 KSaH3fLc+VKMipLhmpn4oS+d9OgAtFMgSIfarofNzvgW+8w9UGlXXze+pdjc8rDEw4Cwu9t iRzqPhcEgmrUi+qGjfDRveDN75P0j/uNnCaR54xk/eWPMSnmaWiGf0CH6hvu0LV5c/TlPX1 LQPD4BflIH/U69/n8xUAcjJUyzcDs9571IQJMVG8ssN43V9mgA= X-QQ-GoodBg: 0 From: Bin Meng To: qemu-devel@nongnu.org Cc: Wilfred Mallawa , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Date: Wed, 7 Dec 2022 18:03:34 +0800 Message-Id: <20221207100335.290481-15-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221207100335.290481-1-bmeng@tinylab.org> References: <20221207100335.290481-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 Received-SPF: pass client-ip=43.154.221.58; envelope-from=bmeng@tinylab.org; helo=bg4.exmail.qq.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org "hartid-base" and "priority-base" are zero by default. There is no need to initialize them to zero again. Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa --- (no changes since v1) hw/riscv/opentitan.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 78f895d773..85ffdac5be 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -173,10 +173,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) /* PLIC */ qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); - qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0); qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); - qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00); qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);