| Message ID | 20221205065303.204095-1-bmeng@tinylab.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Fix mret exception cause when no pmp rule is configured | expand |
On Mon, 2022-12-05 at 14:53 +0800, Bin Meng wrote: > The priv spec v1.12 says: > > If no PMP entry matches an M-mode access, the access succeeds. If > no PMP entry matches an S-mode or U-mode access, but at least one > PMP entry is implemented, the access fails. Failed accesses > generate > an instruction, load, or store access-fault exception. > > At present the exception cause is set to 'illegal instruction' but > should have been 'instruction access fault'. > > Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP > entry is configured") > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > target/riscv/op_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 09f1f5185d..d7af7f056b 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env) > > if (riscv_feature(env, RISCV_FEATURE_PMP) && > !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { > - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, > GETPC()); > + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, > GETPC()); > } > > target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
On Mon, Dec 5, 2022 at 4:54 PM Bin Meng <bmeng@tinylab.org> wrote: > > The priv spec v1.12 says: > > If no PMP entry matches an M-mode access, the access succeeds. If > no PMP entry matches an S-mode or U-mode access, but at least one > PMP entry is implemented, the access fails. Failed accesses generate > an instruction, load, or store access-fault exception. > > At present the exception cause is set to 'illegal instruction' but > should have been 'instruction access fault'. > > Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured") > Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > target/riscv/op_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 09f1f5185d..d7af7f056b 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env) > > if (riscv_feature(env, RISCV_FEATURE_PMP) && > !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { > - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); > } > > target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); > -- > 2.34.1 > >
On Mon, Dec 5, 2022 at 4:54 PM Bin Meng <bmeng@tinylab.org> wrote: > > The priv spec v1.12 says: > > If no PMP entry matches an M-mode access, the access succeeds. If > no PMP entry matches an S-mode or U-mode access, but at least one > PMP entry is implemented, the access fails. Failed accesses generate > an instruction, load, or store access-fault exception. > > At present the exception cause is set to 'illegal instruction' but > should have been 'instruction access fault'. > > Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured") > Signed-off-by: Bin Meng <bmeng@tinylab.org> Thanks! Applied to riscv-to-apply.next Alistair > --- > > target/riscv/op_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 09f1f5185d..d7af7f056b 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env) > > if (riscv_feature(env, RISCV_FEATURE_PMP) && > !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { > - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); > } > > target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); > -- > 2.34.1 > >
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 09f1f5185d..d7af7f056b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env) if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
The priv spec v1.12 says: If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails. Failed accesses generate an instruction, load, or store access-fault exception. At present the exception cause is set to 'illegal instruction' but should have been 'instruction access fault'. Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured") Signed-off-by: Bin Meng <bmeng@tinylab.org> --- target/riscv/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)