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[77.13.7.153]) by smtp.gmail.com with ESMTPSA id de30-20020a1709069bde00b0073d796a1043sm7135444ejc.123.2022.11.16.10.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 10:55:41 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Paolo Bonzini , Huacai Chen , Marcel Apfelbaum , Richard Henderson , Jiaxun Yang , "Michael S. Tsirkin" , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Bernhard Beschow Subject: [RFC PATCH 3/3] hw/isa/vt82c686: Implement PIRQ routing Date: Wed, 16 Nov 2022 19:55:00 +0100 Message-Id: <20221116185500.84019-4-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221116185500.84019-1-shentey@gmail.com> References: <20221116185500.84019-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Both VIA south bridges allow system software to configure the routing of PCI interrupts to ISA interrupts. Implement this to model the real hardware more closely. The implementation is based on hw/isa/piix4.c. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 3f9bd0c04d..21157c669b 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -16,6 +16,7 @@ #include "qemu/osdep.h" #include "hw/isa/vt82c686.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" #include "hw/ide/pci.h" #include "hw/isa/isa.h" @@ -604,6 +605,48 @@ static void via_isa_request_i8259_irq(void *opaque, int irq, int level) qemu_set_irq(s->cpu_intr, level); } +static int via_isa_get_pic_irq(const ViaISAState *s, int irq_num) +{ + switch (irq_num) { + case 0: + return s->dev.config[0x55] >> 4; + + case 1: + return s->dev.config[0x56] & 0xf; + + case 2: + return s->dev.config[0x56] >> 4; + + case 3: + return s->dev.config[0x57] >> 4; + } + + return 0; +} + +static void via_isa_set_pic_irq(void *opaque, int irq_num, int level) +{ + ViaISAState *s = opaque; + PCIBus *bus = pci_get_bus(&s->dev); + int pic_irq; + + /* now we change the pic irq level according to the via irq mappings */ + /* XXX: optimize */ + pic_irq = via_isa_get_pic_irq(s, irq_num); + if (pic_irq < ISA_NUM_IRQS) { + int i, pic_level; + + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level = 0; + for (i = 0; i < PCI_NUM_PINS; i++) { + if (pic_irq == via_isa_get_pic_irq(s, i)) { + pic_level |= pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->isa_irqs[pic_irq], pic_level); + } +} + static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s = VIA_ISA(d); @@ -676,6 +719,9 @@ static void via_isa_realize(PCIDevice *d, Error **errp) if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) { return; } + + pci_bus_irqs(pci_bus, via_isa_set_pic_irq, pci_bus->map_irq, + s, ISA_NUM_IRQS); } /* TYPE_VT82C686B_ISA */