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([103.97.165.210]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a9bc800b00212e5fe09d7sm1212543pjw.10.2022.10.27.09.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 09:48:15 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Date: Thu, 27 Oct 2022 22:17:41 +0530 Message-Id: <20221027164743.194265-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027164743.194265-1-apatel@ventanamicro.com> References: <20221027164743.194265-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c for VSTIP. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 -- target/riscv/time_helper.c | 12 ++++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5d66246c2c..a403825e49 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -617,8 +617,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } - /* No need to update mip for VSTIP */ - mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; vstip = env->vstime_irq ? MIP_VSTIP : 0; if (!qemu_mutex_iothread_locked()) { diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 8cce667dfd..4fb2a471a9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; env->vstime_irq = 1; - riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); } static void riscv_stimer_cb(void *opaque) @@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 1; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + } else { + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); } - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } + /* Clear the [VS|S]TIP bit in mip */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 0; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + } else { + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } - /* Clear the [V]STIP bit in mip */ - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r;