| Message ID | 20221027140207.413084-2-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/boot.c: Set EL3 HXen, vector lengths when direct booting kernel | expand |
On 10/28/22 00:02, Peter Maydell wrote: > When we direct boot a kernel on a CPU which emulates EL3, we need > to set up the EL3 system registers as the Linux kernel documentation > specifies: > https://www.kernel.org/doc/Documentation/arm64/booting.rst > > For SVE and SME this includes: > - ZCR_EL3.LEN must be initialised to the same value for all CPUs the > kernel is executed on. > - SMCR_EL3.LEN must be initialised to the same value for all CPUs the > kernel will execute on. > > Although we are technically compliant with this, the "same value" we > currently use by default is the reset value of 0. This will end up > forcing the guest kernel's SVE and SME vector length to be only the > smallest supported length. > > Initialize the vector length fields to their maximum possible value, > which is 0xf. If the implementation doesn't actually support that > vector length then the effective vector length will be constrained > down to the maximum supported value at point of use. > > This allows the guest to use all the vector lengths the emulated CPU > supports (by programming the _EL2 and _EL1 versions of these > registers.) > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > hw/arm/boot.c | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b0b92af1889..0e4d1e5a816 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -762,10 +762,12 @@ static void do_cpu_reset(void *opaque) } if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; + env->vfp.zcr_el[3] = 0xf; } if (cpu_isar_feature(aa64_sme, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; env->cp15.scr_el3 |= SCR_ENTP2; + env->vfp.smcr_el[3] = 0xf; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot);
When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For SVE and SME this includes: - ZCR_EL3.LEN must be initialised to the same value for all CPUs the kernel is executed on. - SMCR_EL3.LEN must be initialised to the same value for all CPUs the kernel will execute on. Although we are technically compliant with this, the "same value" we currently use by default is the reset value of 0. This will end up forcing the guest kernel's SVE and SME vector length to be only the smallest supported length. Initialize the vector length fields to their maximum possible value, which is 0xf. If the implementation doesn't actually support that vector length then the effective vector length will be constrained down to the maximum supported value at point of use. This allows the guest to use all the vector lengths the emulated CPU supports (by programming the _EL2 and _EL1 versions of these registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+)