| Message ID | 20221027054649.69228-3-mchitale@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Apply KVM policy to ISA extensions | expand |
On Thu, Oct 27, 2022 at 3:50 PM Mayuresh Chitale <mchitale@ventanamicro.com> wrote: > > Currently the ISA string for a CPU is generated from two different > arrays, one for single letter extensions and another for multi letter > extensions. Add all the single letter extensions to the isa_ext_data > array and use it for generating the ISA string. Also drop 'P' and 'Q' > extensions from the list of single letter extensions as those are not > supported yet. > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 41 +++++++++++++++++++++++------------------ > 1 file changed, 23 insertions(+), 18 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e6d9c706bb..35320a8547 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -41,8 +41,6 @@ > (QEMU_VERSION_MICRO)) > #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID > > -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > - > struct isa_ext_data { > const char *name; > bool multi_letter; > @@ -71,6 +69,13 @@ struct isa_ext_data { > * extensions by an underscore. > */ > static const struct isa_ext_data isa_edata_arr[] = { > + ISA_EXT_DATA_ENTRY(i, false, PRIV_VERSION_1_10_0, ext_i), > + ISA_EXT_DATA_ENTRY(e, false, PRIV_VERSION_1_10_0, ext_e), > + ISA_EXT_DATA_ENTRY(m, false, PRIV_VERSION_1_10_0, ext_m), > + ISA_EXT_DATA_ENTRY(a, false, PRIV_VERSION_1_10_0, ext_a), > + ISA_EXT_DATA_ENTRY(f, false, PRIV_VERSION_1_10_0, ext_f), > + ISA_EXT_DATA_ENTRY(d, false, PRIV_VERSION_1_10_0, ext_d), > + ISA_EXT_DATA_ENTRY(c, false, PRIV_VERSION_1_10_0, ext_c), > ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), > ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), > ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), > @@ -1182,16 +1187,23 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > device_class_set_props(dc, riscv_cpu_properties); > } > > -static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str) > { > char *old = *isa_str; > char *new = *isa_str; > int i; > > for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > - if (isa_edata_arr[i].multi_letter && > - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { > - new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); > + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { > + if (isa_edata_arr[i].multi_letter) { > + if (cpu->cfg.short_isa_string) { > + continue; > + } > + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); > + } else { > + new = g_strconcat(old, isa_edata_arr[i].name, NULL); > + } > + > g_free(old); > old = new; > } > @@ -1202,19 +1214,12 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > > char *riscv_isa_string(RISCVCPU *cpu) > { > - int i; > - const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); > + const size_t maxlen = sizeof("rv128"); > char *isa_str = g_new(char, maxlen); > - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > - for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { > - if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { > - *p++ = qemu_tolower(riscv_single_letter_exts[i]); > - } > - } > - *p = '\0'; > - if (!cpu->cfg.short_isa_string) { > - riscv_isa_string_ext(cpu, &isa_str, maxlen); > - } > + > + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > + riscv_isa_string_ext(cpu, &isa_str); > + > return isa_str; > } > > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e6d9c706bb..35320a8547 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -41,8 +41,6 @@ (QEMU_VERSION_MICRO)) #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; - struct isa_ext_data { const char *name; bool multi_letter; @@ -71,6 +69,13 @@ struct isa_ext_data { * extensions by an underscore. */ static const struct isa_ext_data isa_edata_arr[] = { + ISA_EXT_DATA_ENTRY(i, false, PRIV_VERSION_1_10_0, ext_i), + ISA_EXT_DATA_ENTRY(e, false, PRIV_VERSION_1_10_0, ext_e), + ISA_EXT_DATA_ENTRY(m, false, PRIV_VERSION_1_10_0, ext_m), + ISA_EXT_DATA_ENTRY(a, false, PRIV_VERSION_1_10_0, ext_a), + ISA_EXT_DATA_ENTRY(f, false, PRIV_VERSION_1_10_0, ext_f), + ISA_EXT_DATA_ENTRY(d, false, PRIV_VERSION_1_10_0, ext_d), + ISA_EXT_DATA_ENTRY(c, false, PRIV_VERSION_1_10_0, ext_c), ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), @@ -1182,16 +1187,23 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } -static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str) { char *old = *isa_str; char *new = *isa_str; int i; for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].multi_letter && - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { - new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_edata_arr[i].multi_letter) { + if (cpu->cfg.short_isa_string) { + continue; + } + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + } else { + new = g_strconcat(old, isa_edata_arr[i].name, NULL); + } + g_free(old); old = new; } @@ -1202,19 +1214,12 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) char *riscv_isa_string(RISCVCPU *cpu) { - int i; - const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); + const size_t maxlen = sizeof("rv128"); char *isa_str = g_new(char, maxlen); - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); - for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { - if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { - *p++ = qemu_tolower(riscv_single_letter_exts[i]); - } - } - *p = '\0'; - if (!cpu->cfg.short_isa_string) { - riscv_isa_string_ext(cpu, &isa_str, maxlen); - } + + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); + riscv_isa_string_ext(cpu, &isa_str); + return isa_str; }
Currently the ISA string for a CPU is generated from two different arrays, one for single letter extensions and another for multi letter extensions. Add all the single letter extensions to the isa_ext_data array and use it for generating the ISA string. Also drop 'P' and 'Q' extensions from the list of single letter extensions as those are not supported yet. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> --- target/riscv/cpu.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-)