@@ -956,82 +956,6 @@ enum {
OPC_NMSUB_PS = 0x3E | OPC_CP3,
};
-/*
- * MMI (MultiMedia Instruction) encodings
- * ======================================
- *
- * MMI instructions encoding table keys:
- *
- * * This code is reserved for future use. An attempt to execute it
- * causes a Reserved Instruction exception.
- * % This code indicates an instruction class. The instruction word
- * must be further decoded by examining additional tables that show
- * the values for other instruction fields.
- * # This code is reserved for the unsupported instructions DMULT,
- * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
- * to execute it causes a Reserved Instruction exception.
- *
- * MMI instructions encoded by opcode field (MMI, LQ, SQ):
- *
- * 31 26 0
- * +--------+----------------------------------------+
- * | opcode | |
- * +--------+----------------------------------------+
- *
- * opcode bits 28..26
- * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
- * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
- * -------+-------+-------+-------+-------+-------+-------+-------+-------
- * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
- * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
- * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
- * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
- * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
- * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
- * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
- * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
- */
-
-enum {
- MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
- MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
-};
-
-/*
- * MMI instructions with opcode field = MMI:
- *
- * 31 26 5 0
- * +--------+-------------------------------+--------+
- * | MMI | |function|
- * +--------+-------------------------------+--------+
- *
- * function bits 2..0
- * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
- * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
- * -------+-------+-------+-------+-------+-------+-------+-------+-------
- * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
- * 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
- * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
- * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
- * 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
- * 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
- * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
- * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
- */
-
-#define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
-enum {
- MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
- MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
- MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
- MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
- MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */
- MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
- MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI,
- MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI,
-};
-
-
/* global register indices */
TCGv cpu_gpr[32], cpu_PC;
/*
@@ -3270,65 +3194,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_temp_free(t1);
}
-#if defined(TARGET_MIPS64)
-static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
-{
- TCGv t0, t1;
-
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
-
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
-
- switch (opc) {
- case MMI_OPC_DIV1:
- {
- TCGv t2 = tcg_temp_new();
- TCGv t3 = tcg_temp_new();
- tcg_gen_ext32s_tl(t0, t0);
- tcg_gen_ext32s_tl(t1, t1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
- tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
- tcg_gen_and_tl(t2, t2, t3);
- tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
- tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
- tcg_gen_div_tl(cpu_LO[1], t0, t1);
- tcg_gen_rem_tl(cpu_HI[1], t0, t1);
- tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
- tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
- }
- break;
- case MMI_OPC_DIVU1:
- {
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
- tcg_gen_divu_tl(cpu_LO[1], t0, t1);
- tcg_gen_remu_tl(cpu_HI[1], t0, t1);
- tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
- tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
- }
- break;
- default:
- MIPS_INVAL("div1 TX79");
- gen_reserved_instruction(ctx);
- goto out;
- }
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-#endif
-
static void gen_muldiv(DisasContext *ctx, uint32_t opc,
int acc, int rs, int rt)
{
@@ -3521,138 +3386,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
-/*
- * These MULT[U] and MADD[U] instructions implemented in for example
- * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
- * architectures are special three-operand variants with the syntax
- *
- * MULT[U][1] rd, rs, rt
- *
- * such that
- *
- * (rd, LO, HI) <- rs * rt
- *
- * and
- *
- * MADD[U][1] rd, rs, rt
- *
- * such that
- *
- * (rd, LO, HI) <- (LO, HI) + rs * rt
- *
- * where the low-order 32-bits of the result is placed into both the
- * GPR rd and the special register LO. The high-order 32-bits of the
- * result is placed into the special register HI.
- *
- * If the GPR rd is omitted in assembly language, it is taken to be 0,
- * which is the zero register that always reads as 0.
- */
-static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
- int rd, int rs, int rt)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- int acc = 0;
-
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
-
- switch (opc) {
- case MMI_OPC_MULT1:
- acc = 1;
- /* Fall through */
- case OPC_MULT:
- {
- TCGv_i32 t2 = tcg_temp_new_i32();
- TCGv_i32 t3 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t2, t0);
- tcg_gen_trunc_tl_i32(t3, t1);
- tcg_gen_muls2_i32(t2, t3, t2, t3);
- if (rd) {
- tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
- }
- tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
- tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
- }
- break;
- case MMI_OPC_MULTU1:
- acc = 1;
- /* Fall through */
- case OPC_MULTU:
- {
- TCGv_i32 t2 = tcg_temp_new_i32();
- TCGv_i32 t3 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t2, t0);
- tcg_gen_trunc_tl_i32(t3, t1);
- tcg_gen_mulu2_i32(t2, t3, t2, t3);
- if (rd) {
- tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
- }
- tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
- tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t3);
- }
- break;
- case MMI_OPC_MADD1:
- acc = 1;
- /* Fall through */
- case MMI_OPC_MADD:
- {
- TCGv_i64 t2 = tcg_temp_new_i64();
- TCGv_i64 t3 = tcg_temp_new_i64();
-
- tcg_gen_ext_tl_i64(t2, t0);
- tcg_gen_ext_tl_i64(t3, t1);
- tcg_gen_mul_i64(t2, t2, t3);
- tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
- tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
- gen_move_low32(cpu_LO[acc], t2);
- gen_move_high32(cpu_HI[acc], t2);
- if (rd) {
- gen_move_low32(cpu_gpr[rd], t2);
- }
- tcg_temp_free_i64(t2);
- }
- break;
- case MMI_OPC_MADDU1:
- acc = 1;
- /* Fall through */
- case MMI_OPC_MADDU:
- {
- TCGv_i64 t2 = tcg_temp_new_i64();
- TCGv_i64 t3 = tcg_temp_new_i64();
-
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_extu_tl_i64(t2, t0);
- tcg_gen_extu_tl_i64(t3, t1);
- tcg_gen_mul_i64(t2, t2, t3);
- tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
- tcg_gen_add_i64(t2, t2, t3);
- tcg_temp_free_i64(t3);
- gen_move_low32(cpu_LO[acc], t2);
- gen_move_high32(cpu_HI[acc], t2);
- if (rd) {
- gen_move_low32(cpu_gpr[rd], t2);
- }
- tcg_temp_free_i64(t2);
- }
- break;
- default:
- MIPS_INVAL("mul/madd TXx9");
- gen_reserved_instruction(ctx);
- goto out;
- }
-
- out:
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
static void gen_cl(DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
@@ -12920,53 +12653,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
}
}
-static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
-{
- int rs = extract32(ctx->opcode, 21, 5);
- int rt = extract32(ctx->opcode, 16, 5);
- int rd = extract32(ctx->opcode, 11, 5);
- uint32_t op1 = MASK_SPECIAL(ctx->opcode);
-
- switch (op1) {
- case OPC_MOVN: /* Conditional move */
- case OPC_MOVZ:
- gen_cond_move(ctx, op1, rd, rs, rt);
- break;
- case OPC_MFHI: /* Move from HI/LO */
- case OPC_MFLO:
- gen_HILO(ctx, op1, 0, rd);
- break;
- case OPC_MTHI:
- case OPC_MTLO: /* Move to HI/LO */
- gen_HILO(ctx, op1, 0, rs);
- break;
- case OPC_MULT:
- case OPC_MULTU:
- gen_mul_txx9(ctx, op1, rd, rs, rt);
- break;
- case OPC_DIV:
- case OPC_DIVU:
- gen_muldiv(ctx, op1, 0, rs, rt);
- break;
-#if defined(TARGET_MIPS64)
- case OPC_DMULT:
- case OPC_DMULTU:
- case OPC_DDIV:
- case OPC_DDIVU:
- check_insn_opc_user_only(ctx, INSN_R5900);
- gen_muldiv(ctx, op1, 0, rs, rt);
- break;
-#endif
- case OPC_JR:
- gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
- break;
- default: /* Invalid */
- MIPS_INVAL("special_tx79");
- gen_reserved_instruction(ctx);
- break;
- }
-}
-
static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd;
@@ -13016,6 +12702,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_DDIV:
case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3);
+ check_insn_opc_user_only(ctx, INSN_R5900);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
break;
@@ -13231,8 +12918,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
default:
if (ctx->insn_flags & ISA_MIPS_R6) {
decode_opc_special_r6(env, ctx);
- } else if (ctx->insn_flags & INSN_R5900) {
- decode_opc_special_tx79(env, ctx);
} else {
decode_opc_special_legacy(env, ctx);
}
@@ -13911,85 +13596,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
-
-#if defined(TARGET_MIPS64)
-
-static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
-{
- uint32_t opc = MASK_MMI(ctx->opcode);
- int rs = extract32(ctx->opcode, 21, 5);
- int rt = extract32(ctx->opcode, 16, 5);
- int rd = extract32(ctx->opcode, 11, 5);
-
- switch (opc) {
- case MMI_OPC_MULT1:
- case MMI_OPC_MULTU1:
- case MMI_OPC_MADD:
- case MMI_OPC_MADDU:
- case MMI_OPC_MADD1:
- case MMI_OPC_MADDU1:
- gen_mul_txx9(ctx, opc, rd, rs, rt);
- break;
- case MMI_OPC_DIV1:
- case MMI_OPC_DIVU1:
- gen_div1_tx79(ctx, opc, rs, rt);
- break;
- default:
- MIPS_INVAL("TX79 MMI class");
- gen_reserved_instruction(ctx);
- break;
- }
-}
-
-static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
-{
- gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
-}
-
-/*
- * The TX79-specific instruction Store Quadword
- *
- * +--------+-------+-------+------------------------+
- * | 011111 | base | rt | offset | SQ
- * +--------+-------+-------+------------------------+
- * 6 5 5 16
- *
- * has the same opcode as the Read Hardware Register instruction
- *
- * +--------+-------+-------+-------+-------+--------+
- * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
- * +--------+-------+-------+-------+-------+--------+
- * 6 5 5 5 5 6
- *
- * that is required, trapped and emulated by the Linux kernel. However, all
- * RDHWR encodings yield address error exceptions on the TX79 since the SQ
- * offset is odd. Therefore all valid SQ instructions can execute normally.
- * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
- * between SQ and RDHWR, as the Linux kernel does.
- */
-static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
-{
- int base = extract32(ctx->opcode, 21, 5);
- int rt = extract32(ctx->opcode, 16, 5);
- int offset = extract32(ctx->opcode, 0, 16);
-
-#ifdef CONFIG_USER_ONLY
- uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
- uint32_t op2 = extract32(ctx->opcode, 6, 5);
-
- if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
- int rd = extract32(ctx->opcode, 11, 5);
-
- gen_rdhwr(ctx, rt, rd, 0);
- return;
- }
-#endif
-
- gen_mmi_sq(ctx, base, rt, offset);
-}
-
-#endif
-
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@@ -14160,12 +13766,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
-#if defined(TARGET_MIPS64)
- if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
- decode_mmi(env, ctx);
- break;
- }
-#endif
if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) {
gen_arith(ctx, OPC_MUL, rd, rs, rt);
@@ -14177,15 +13777,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special2_legacy(env, ctx);
break;
case OPC_SPECIAL3:
-#if defined(TARGET_MIPS64)
- if (ctx->insn_flags & INSN_R5900) {
- decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
- } else {
- decode_opc_special3(env, ctx);
- }
-#else
decode_opc_special3(env, ctx);
-#endif
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
@@ -33,6 +33,20 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs
+# MUL
+# MULT/MULTU are reusing MIPS SPECIAL MAJOR_OP
+MULT 000000 ..... ..... ..... 00000 011000 @rs_rt_rd
+MULTU 000000 ..... ..... ..... 00000 011001 @rs_rt_rd
+# Rests are using SPECIAL2 encoding
+MADD 011100 ..... ..... ..... 00000 000000 @rs_rt_rd
+MADDU 011100 ..... ..... ..... 00000 000001 @rs_rt_rd
+MULT1 011100 ..... ..... ..... 00000 011000 @rs_rt_rd
+MULTU1 011100 ..... ..... ..... 00000 011001 @rs_rt_rd
+DIV1 011100 ..... ..... ..... 00000 011010 @rs_rt_rd
+DIVU1 011100 ..... ..... ..... 00000 011011 @rs_rt_rd
+MADD1 011100 ..... ..... ..... 00000 100000 @rs_rt_rd
+MADDU1 011100 ..... ..... ..... 00000 100001 @rs_rt_rd
+
# MMI0
PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
@@ -369,7 +369,7 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
return true;
}
-static bool trans_SQ(DisasContext *ctx, arg_i *a)
+static bool gen_SQ(DisasContext *ctx, arg_i *a)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv addr = tcg_temp_new();
@@ -396,6 +396,32 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
return true;
}
+#define RDHWR_MASK(op) (op & 0xffe0063f)
+#define OPC_RDHWR 0x7c00003b
+
+static bool trans_SQ(DisasContext *ctx, arg_i *a)
+{
+#ifdef CONFIG_USER_ONLY
+ /*
+ * that is required, trapped and emulated by the Linux kernel. However, all
+ * RDHWR encodings yield address error exceptions on the TX79 since the SQ
+ * offset is odd. Therefore all valid SQ instructions can execute normally.
+ * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
+ * between SQ and RDHWR, as the Linux kernel does.
+ */
+ if (RDHWR_MASK(ctx->opcode) == OPC_RDHWR) {
+ int rd = extract32(ctx->opcode, 11, 5);
+ int rt = extract32(ctx->opcode, 16, 5);
+ int sel = extract32(ctx->opcode, 6, 3);
+
+ gen_rdhwr(ctx, rt, rd, sel);
+ return true;
+ }
+#endif
+
+ return gen_SQ(ctx, a);
+}
+
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
@@ -683,3 +709,180 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a)
return true;
}
+
+/*
+ * These MULT[U] and MADD[U] instructions implemented in for example
+ * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * architectures are special three-operand variants with the syntax
+ *
+ * MULT[U][1] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- rs * rt
+ *
+ * and
+ *
+ * MADD[U][1] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- (LO, HI) + rs * rt
+ *
+ * where the low-order 32-bits of the result is placed into both the
+ * GPR rd and the special register LO. The high-order 32-bits of the
+ * result is placed into the special register HI.
+ *
+ * If the GPR rd is omitted in assembly language, it is taken to be 0,
+ * which is the zero register that always reads as 0.
+ */
+
+static bool gen_mult(DisasContext *ctx, arg_r *a, int acc,
+ void (*func)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv src1 = get_gpr(ctx, a->rs, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rt, EXT_NONE);
+ TCGv dst_lo = dest_lo(ctx, acc);
+ TCGv dst_hi = dest_hi(ctx, acc);
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t1, src1);
+ tcg_gen_trunc_tl_i32(t2, src2);
+
+ func(t1, t2, t1, t2);
+
+ tcg_gen_ext_i32_tl(dst_lo, t1);
+ tcg_gen_ext_i32_tl(dst_hi, t2);
+
+ gen_set_gpr(a->rd, dst_lo, EXT_NONE);
+ gen_set_lo(acc, dst_lo, EXT_NONE);
+ gen_set_hi(acc, dst_hi, EXT_NONE);
+
+ return true;
+}
+
+TRANS_6R(MULT, gen_mult, 0, tcg_gen_muls2_i32)
+TRANS_6R(MULTU, gen_mult, 0, tcg_gen_mulu2_i32)
+TRANS_6R(MULT1, gen_mult, 1, tcg_gen_muls2_i32)
+TRANS_6R(MULTU1, gen_mult, 1, tcg_gen_mulu2_i32)
+
+static bool gen_mul_addsub(DisasContext *ctx, arg_r *a, int acc, DisasExtend ext,
+ void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv src1 = get_gpr(ctx, a->rs, ext);
+ TCGv src2 = get_gpr(ctx, a->rt, ext);
+ TCGv_i64 src3 = get_hilo(ctx, acc);
+ TCGv_i64 dst = dest_hilo(ctx, acc);
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ switch (ext) {
+ case EXT_SIGN:
+ tcg_gen_ext_tl_i64(t2, src1);
+ tcg_gen_ext_tl_i64(t3, src2);
+ break;
+ case EXT_ZERO:
+ tcg_gen_extu_tl_i64(t2, src1);
+ tcg_gen_extu_tl_i64(t3, src2);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+
+ tcg_gen_mul_i64(dst, t2, t3);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+ func(dst, dst, src3);
+
+ gen_set_hilo(acc, dst);
+
+ return true;
+}
+
+TRANS(MADD, gen_mul_addsub, 0, EXT_SIGN, tcg_gen_add_i64)
+TRANS(MADDU, gen_mul_addsub, 0, EXT_ZERO, tcg_gen_add_i64)
+TRANS(MADD1, gen_mul_addsub, 1, EXT_SIGN, tcg_gen_add_i64)
+TRANS(MADDU1, gen_mul_addsub, 1, EXT_ZERO, tcg_gen_add_i64)
+
+static bool gen_div(DisasContext *ctx, arg_r *a, int acc,
+ DisasExtend src_ext, DisasExtend dst_ext)
+{
+ TCGv temp1, temp2, zero, one, mone, min;
+ TCGv src1 = get_gpr(ctx, a->rs, src_ext);
+ TCGv src2 = get_gpr(ctx, a->rt, src_ext);
+ TCGv dst_lo = dest_lo(ctx, acc);
+ TCGv dst_hi = dest_hi(ctx, acc);
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+ /*
+ * If overflow, set temp2 to 1, else source2.
+ * This produces the required result of min.
+ */
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, src1, min);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, src2, mone);
+ tcg_gen_and_tl(temp1, temp1, temp2);
+ tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, src2);
+
+ /*
+ * If div by zero, set temp1 to -1 and temp2 to 1 to
+ * produce the required result of -1.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp1, src2, zero, mone, src1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, src2, zero, one, src2);
+
+ tcg_gen_div_tl(dst_lo, temp1, temp2);
+ tcg_gen_rem_tl(dst_hi, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+
+ gen_set_lo(acc, dst_lo, dst_ext);
+ gen_set_hi(acc, dst_hi, dst_ext);
+
+ return true;
+}
+
+static bool gen_divu(DisasContext *ctx, arg_r *a, int acc,
+ DisasExtend src_ext, DisasExtend dst_ext)
+{
+ TCGv temp1, temp2, zero, one, max;
+ TCGv src1 = get_gpr(ctx, a->rs, src_ext);
+ TCGv src2 = get_gpr(ctx, a->rt, src_ext);
+ TCGv dst_lo = dest_lo(ctx, acc);
+ TCGv dst_hi = dest_hi(ctx, acc);
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ max = tcg_constant_tl(~0);
+
+ /*
+ * If div by zero, set temp1 to max and temp2 to 1 to
+ * produce the required result of max.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp1, src2, zero, max, src1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, src2, zero, one, src2);
+
+ tcg_gen_divu_tl(dst_lo, temp1, temp2);
+ tcg_gen_remu_tl(dst_hi, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
+
+ gen_set_lo(acc, dst_lo, dst_ext);
+ gen_set_hi(acc, dst_hi, dst_ext);
+
+ return true;
+}
+
+TRANS(DIV1, gen_div, 1, EXT_SIGN, EXT_SIGN)
+TRANS(DIVU1, gen_divu, 1, EXT_ZERO, EXT_SIGN)
Move MUL family instructions into decodetree. Also implement RDHWR emulation for user instructions in decodetree SQ translation. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- target/mips/tcg/translate.c | 410 +------------------------------ target/mips/tcg/tx79.decode | 14 ++ target/mips/tcg/tx79_translate.c | 205 +++++++++++++++- 3 files changed, 219 insertions(+), 410 deletions(-)