From patchwork Thu Oct 6 03:38:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1686606 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=X1w2Tm5e; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Mjcw51YLjz20Vp for ; Thu, 6 Oct 2022 14:52:37 +1100 (AEDT) Received: from localhost ([::1]:44442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ogHw3-0002Q8-3K for incoming@patchwork.ozlabs.org; Wed, 05 Oct 2022 23:52:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ogHiv-00035r-84 for qemu-devel@nongnu.org; Wed, 05 Oct 2022 23:39:01 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:46864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ogHiq-0002vE-2s for qemu-devel@nongnu.org; Wed, 05 Oct 2022 23:39:00 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 78so709835pgb.13 for ; Wed, 05 Oct 2022 20:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=/HSVS8Osbt4Mrz1BcjPrljW8HECtJ7Rwutl3njSap2A=; b=X1w2Tm5ebiewv1t+LvPKIP7sPfY7NJR7hId/pggqlXPmxBdQM6lQz9RALiSlK6wvNL 5xGcgebreUHdILzZSXvrJTLnQEMFcSTAQPy4ZF/4u1QTbn10QUB0+rB7XPUs1dQxZDUM odQI2+3qSPs1WHix+T/MMVcQ5svrUiT2UrPH7jf00ERLnvSbIIL/D3VRdCVyuBUEDr2Y OnLT64zEHPHN8QFsnUQ/vsO0BcJkWETM5STjKEDmzKAtvIYuEVMQ9ntaomfM4WjgAXwN nxHXVNIuKD9sDgfJ4uOW7FlCk+fRZJ7qbKRYPq56Ot/S9mHBkL5yVeFzSIIAXA7UhRkv 6/Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=/HSVS8Osbt4Mrz1BcjPrljW8HECtJ7Rwutl3njSap2A=; b=P8H5edYNJ7G0gsLWrxTz1z34uQI2+Icm9L5WK0m1zt5X1wu7IA6YPFH4jjxMxkZYlA nJZmi0FmB6JvPeeRZarejBOl+aj/Jr2tl8Q866yS5efBGpdbX4fasXq6qt4pDzvzBwe/ eRgPr8us3/4Q/RkCfgLksThgOIEwx0HKEl76ucM9kzonawIzZhE/7WFS33ol0qDhtaqW qa+nyGxakeapUQEZaWgg1TsYvyhEzlr4qTJrLFvCSv5q16Le1k3RlMarPv8EXiXGKSI/ konsTstZQo01QUI0AAClVjqmpM506nDo9pRMPETU+BoxAaPxDm+pg69+C5E1TE1u9AkV 0rHw== X-Gm-Message-State: ACrzQf1dHehV1hmYtb8a0PXF0sEKmUh3iDt+SAbI/jMudGNRTXgN8Gje d3uH1IoyuoFWbgDqwNz+Dxwiv3OKNOAoCQ== X-Google-Smtp-Source: AMsMyM6ppeYsZDxSMgjG2bfI4B6sL/XOjkWS9b25gpMMGh7AdNIGT5rSjrtRlCetQdKb6hdRuYmIYA== X-Received: by 2002:a65:6cce:0:b0:439:49b5:48b8 with SMTP id g14-20020a656cce000000b0043949b548b8mr2649032pgw.514.1665027534262; Wed, 05 Oct 2022 20:38:54 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id t11-20020a63534b000000b0043014f9a4c9sm539831pgl.93.2022.10.05.20.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 7/9] target/arm: Introduce gen_pc_plus_diff for aarch64 Date: Wed, 5 Oct 2022 20:38:44 -0700 Message-Id: <20221006033846.1178422-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006033846.1178422-1-richard.henderson@linaro.org> References: <20221006033846.1178422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 005fd767fb..28a417fb2b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,14 @@ static void reset_btype(DisasContext *s) } } +static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff) +{ + tcg_gen_movi_i64(dest, s->pc_curr + diff); +} + void gen_a64_update_pc(DisasContext *s, target_long diff) { - tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_pc, diff); } /* @@ -1368,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) if (insn & (1U << 31)) { /* BL Branch with link */ - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); } /* B Branch / BL Branch with link */ @@ -2309,11 +2314,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; case 8: /* BRAA */ @@ -2336,11 +2347,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } else { dst = cpu_reg(s, rn); } - gen_a64_set_pc(s, dst); /* BLRAA also needs to load return address */ if (opc == 9) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; case 4: /* ERET */ @@ -2908,7 +2925,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) tcg_rt = cpu_reg(s, rt); - clean_addr = tcg_constant_i64(s->pc_curr + imm); + clean_addr = new_tmp_a64(s); + gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -4252,23 +4270,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn) static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { unsigned int page, rd; - uint64_t base; - uint64_t offset; + int64_t offset; page = extract32(insn, 31, 1); /* SignExtend(immhi:immlo) -> offset */ offset = sextract64(insn, 5, 19); offset = offset << 2 | extract32(insn, 29, 2); rd = extract32(insn, 0, 5); - base = s->pc_curr; if (page) { /* ADRP (page based) */ - base &= ~0xfff; offset <<= 12; + /* The page offset is ok for TARGET_TB_PCREL. */ + offset -= s->pc_curr & 0xfff; } - tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); + gen_pc_plus_diff(s, cpu_reg(s, rd), offset); } /*